Merge tag 'drm-intel-next-2015-03-13-merge' of git://anongit.freedesktop.org/drm-intel into drm-next

drm-intel-next-2015-03-13-rebased:
- EU count report param for gen9+ (Jeff McGee)
- piles of pll/wm/... fixes for chv, finally out of preliminary hw support
  (Ville, Vijay)
- gen9 rps support from Akash
- more work to move towards atomic from Matt, Ander and others
- runtime pm support for skl (Damien)
- edp1.4 intermediate link clock support (Sonika)
- use frontbuffer tracking for fbc (Paulo)
- remove ilk rc6 (John Harrison)
- a bunch of smaller things and fixes all over

Includes backmerge because git rerere couldn't keep up any more.

* tag 'drm-intel-next-2015-03-13-merge' of git://anongit.freedesktop.org/drm-intel: (366 commits)
  drm/i915: Make sure the primary plane is enabled before reading out the fb state
  drm/i915: Update DRIVER_DATE to 20150313
  drm/i915: Fix vmap_batch page iterator overrun
  drm/i915: Export total subslice and EU counts
  drm/i915: redefine WARN_ON_ONCE to include the condition
  drm/i915/skl: Implement WaDisableHBR2
  drm/i915: Remove the preliminary_hw_support shackles from CHV
  drm/i915: Read CHV_PLL_DW8 from the correct offset
  drm/i915: Rewrite IVB FDI bifurcation conflict checks
  drm/i915: Rewrite some some of the FDI lane checks
  drm/i915/skl: Enable the RPS interrupts programming
  drm/i915/skl: Enabling processing of Turbo interrupts
  drm/i915/skl: Updated the i915_frequency_info debugfs function
  drm/i915: Simplify the way BC bifurcation state consistency is kept
  drm/i915/skl: Updated the act_freq_mhz_show sysfs function
  drm/i915/skl: Updated the gen9_enable_rps function
  drm/i915/skl: Updated the gen6_rps_limits function
  drm/i915/skl: Restructured the gen6_set_rps_thresholds function
  drm/i915/skl: Updated the gen6_set_rps function
  drm/i915/skl: Updated the gen6_init_rps_frequencies function
  ...

1 files changed, 25 insertions, 24 deletions

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index f2e47fd56751..613372375ada 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -208,40 +208,41 @@
 #define INTEL_VLV_D_IDS(info) \
         INTEL_VGA_DEVICE(0x0155, info)
 
-#define _INTEL_BDW_M(gt, id, info) \
-        INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
-#define _INTEL_BDW_D(gt, id, info) \
-        INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
-
-#define _INTEL_BDW_M_IDS(gt, info) \
-        _INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \
-        _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
-        _INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \
-        _INTEL_BDW_M(gt, 0x160E, info) /* ULX */
-
-#define _INTEL_BDW_D_IDS(gt, info) \
-        _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
-        _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
-
-#define INTEL_BDW_GT12M_IDS(info) \
-        _INTEL_BDW_M_IDS(1, info), \
-        _INTEL_BDW_M_IDS(2, info)
+#define INTEL_BDW_GT12M_IDS(info)  \
+        INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+        INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+        INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+        INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+        INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+        INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+        INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+        INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
 
 #define INTEL_BDW_GT12D_IDS(info) \
-        _INTEL_BDW_D_IDS(1, info), \
-        _INTEL_BDW_D_IDS(2, info)
+        INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+        INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
+        INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+        INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 
 #define INTEL_BDW_GT3M_IDS(info) \
-        _INTEL_BDW_M_IDS(3, info)
+        INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
+        INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+        INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
+        INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
 
 #define INTEL_BDW_GT3D_IDS(info) \
-        _INTEL_BDW_D_IDS(3, info)
+        INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
+        INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 
 #define INTEL_BDW_RSVDM_IDS(info) \
-        _INTEL_BDW_M_IDS(4, info)
+        INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
+        INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+        INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
+        INTEL_VGA_DEVICE(0x163E, info)  /* ULX */
 
 #define INTEL_BDW_RSVDD_IDS(info) \
-        _INTEL_BDW_D_IDS(4, info)
+        INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
+        INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 
 #define INTEL_BDW_M_IDS(info) \
         INTEL_BDW_GT12M_IDS(info), \