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authorDave Airlie <airlied@redhat.com>2013-09-09 22:36:55 -0400
committerDave Airlie <airlied@redhat.com>2013-09-09 22:36:55 -0400
commit48016851c89fcb1e9ea4daa7ace142e95f7875fe (patch)
tree11c2ce83e2d618ae4fc5915ed82d60da77cd9bfa /include/drm
parent86a7e1224a68511d3a1ae0b7e11581b9d37723ae (diff)
parent6e1b4fdad5157bb9e88777d525704aba24389bee (diff)
Merge tag 'drm-intel-fixes-2013-09-06' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
- Early stolen mem reservation from Jesse in x86 boot code. Acked by Ingo and hpa. This was ready much earlier but somehow I've thought it'd go in through x86 trees, hence why this is late. Avoids the pci resource code to plant mmiobars in the middle of stolen mem and other ugliness. - vgaarb improvements from Alex Williamson plus the fix from Ville for the vgacon->fbcon smooth transition "feature". - Render pageflips on ivb/hsw to avoid stalls due to the ring switching when only flipping on the blitter (Chris). - Deadlock fixes around our flush_workqueue which crept back in - lockdep isn't clever enough :( - Shrinker recursion fix from Chris - this is the thing that blew the vma patches from Ben I've taken out of 3.12. - Fixup for the relocation refactoring. Also an igt testcase to make sure we don't break this again. - Pile of smaller fixups all over, shortlog has full details. * tag 'drm-intel-fixes-2013-09-06' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits) drm/i915: Delay disabling of VGA memory until vgacon->fbcon handoff is done drm/i915: try not to lose backlight CBLV precision drm/i915: Confine page flips to BCS on Valleyview drm/i915: Skip stolen region initialisation if none is reserved drm/i915: fix gpu hang vs. flip stall deadlocks drm/i915: Hold an object reference whilst we shrink it drm/i915: fix i9xx_crtc_clock_get for multiplied pixels drm/i915: handle sdvo input pixel multiplier correctly again drm/i915: fix hpd work vs. flush_work in the pageflip code deadlock drm/i915: fix up the relocate_entry refactoring drm/i915: Fix pipe config warnings when dealing with LVDS fixed mode drm/i915: Don't call sg_free_table() if sg_alloc_table() fails i915: Update VGA arbiter support for newer devices vgaarb: Fix VGA decodes changes vgaarb: Don't disable resources that are not owned drm/i915: Pin pages whilst mapping the dma-buf drm/i915: enable trickle feed on Haswell x86: add early quirk for reserving Intel graphics stolen memory v5 drm/i915: split PCI IDs out into i915_drm.h v4 i915_gem: Convert kmem_cache_alloc(...GFP_ZERO) to kmem_cache_zalloc ...
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/i915_drm.h34
-rw-r--r--include/drm/i915_pciids.h211
2 files changed, 245 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 63d609d8a3f6..3abfa6ea226e 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -26,6 +26,7 @@
26#ifndef _I915_DRM_H_ 26#ifndef _I915_DRM_H_
27#define _I915_DRM_H_ 27#define _I915_DRM_H_
28 28
29#include <drm/i915_pciids.h>
29#include <uapi/drm/i915_drm.h> 30#include <uapi/drm/i915_drm.h>
30 31
31/* For use by IPS driver */ 32/* For use by IPS driver */
@@ -34,4 +35,37 @@ extern bool i915_gpu_raise(void);
34extern bool i915_gpu_lower(void); 35extern bool i915_gpu_lower(void);
35extern bool i915_gpu_busy(void); 36extern bool i915_gpu_busy(void);
36extern bool i915_gpu_turbo_disable(void); 37extern bool i915_gpu_turbo_disable(void);
38
39/*
40 * The Bridge device's PCI config space has information about the
41 * fb aperture size and the amount of pre-reserved memory.
42 * This is all handled in the intel-gtt.ko module. i915.ko only
43 * cares about the vga bit for the vga rbiter.
44 */
45#define INTEL_GMCH_CTRL 0x52
46#define INTEL_GMCH_VGA_DISABLE (1 << 1)
47#define SNB_GMCH_CTRL 0x50
48#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
49#define SNB_GMCH_GGMS_MASK 0x3
50#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
51#define SNB_GMCH_GMS_MASK 0x1f
52
53#define I830_GMCH_CTRL 0x52
54
55#define I855_GMCH_GMS_MASK 0xF0
56#define I855_GMCH_GMS_STOLEN_0M 0x0
57#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
58#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
59#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
60#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
61#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
62#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
63#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
64#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
65#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
66#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
67#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
68#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
69#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
70
37#endif /* _I915_DRM_H_ */ 71#endif /* _I915_DRM_H_ */
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
new file mode 100644
index 000000000000..8a10f5c354e6
--- /dev/null
+++ b/include/drm/i915_pciids.h
@@ -0,0 +1,211 @@
1/*
2 * Copyright 2013 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#ifndef _I915_PCIIDS_H
26#define _I915_PCIIDS_H
27
28/*
29 * A pci_device_id struct {
30 * __u32 vendor, device;
31 * __u32 subvendor, subdevice;
32 * __u32 class, class_mask;
33 * kernel_ulong_t driver_data;
34 * };
35 * Don't use C99 here because "class" is reserved and we want to
36 * give userspace flexibility.
37 */
38#define INTEL_VGA_DEVICE(id, info) { \
39 0x8086, id, \
40 ~0, ~0, \
41 0x030000, 0xff0000, \
42 (unsigned long) info }
43
44#define INTEL_QUANTA_VGA_DEVICE(info) { \
45 0x8086, 0x16a, \
46 0x152d, 0x8990, \
47 0x030000, 0xff0000, \
48 (unsigned long) info }
49
50#define INTEL_I830_IDS(info) \
51 INTEL_VGA_DEVICE(0x3577, info)
52
53#define INTEL_I845G_IDS(info) \
54 INTEL_VGA_DEVICE(0x2562, info)
55
56#define INTEL_I85X_IDS(info) \
57 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
58 INTEL_VGA_DEVICE(0x358e, info)
59
60#define INTEL_I865G_IDS(info) \
61 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
62
63#define INTEL_I915G_IDS(info) \
64 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
65 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
66
67#define INTEL_I915GM_IDS(info) \
68 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
69
70#define INTEL_I945G_IDS(info) \
71 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
72
73#define INTEL_I945GM_IDS(info) \
74 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
75 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
76
77#define INTEL_I965G_IDS(info) \
78 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
79 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
80 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
81 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
82
83#define INTEL_G33_IDS(info) \
84 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
85 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
86 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
87
88#define INTEL_I965GM_IDS(info) \
89 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
90 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
91
92#define INTEL_GM45_IDS(info) \
93 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
94
95#define INTEL_G45_IDS(info) \
96 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
97 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
98 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
99 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
100 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
101 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
102
103#define INTEL_PINEVIEW_IDS(info) \
104 INTEL_VGA_DEVICE(0xa001, info), \
105 INTEL_VGA_DEVICE(0xa011, info)
106
107#define INTEL_IRONLAKE_D_IDS(info) \
108 INTEL_VGA_DEVICE(0x0042, info)
109
110#define INTEL_IRONLAKE_M_IDS(info) \
111 INTEL_VGA_DEVICE(0x0046, info)
112
113#define INTEL_SNB_D_IDS(info) \
114 INTEL_VGA_DEVICE(0x0102, info), \
115 INTEL_VGA_DEVICE(0x0112, info), \
116 INTEL_VGA_DEVICE(0x0122, info), \
117 INTEL_VGA_DEVICE(0x010A, info)
118
119#define INTEL_SNB_M_IDS(info) \
120 INTEL_VGA_DEVICE(0x0106, info), \
121 INTEL_VGA_DEVICE(0x0116, info), \
122 INTEL_VGA_DEVICE(0x0126, info)
123
124#define INTEL_IVB_M_IDS(info) \
125 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
126 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
127
128#define INTEL_IVB_D_IDS(info) \
129 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
130 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
131 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
132 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
133
134#define INTEL_IVB_Q_IDS(info) \
135 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
136
137#define INTEL_HSW_D_IDS(info) \
138 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
139 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
140 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
141 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
142 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
143 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
144 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
145 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
146 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
147 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
148 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
149 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
150 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
151 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
152 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
153 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
154 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
155 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
156 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
157 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
158 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
159 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
160 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
161 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
162 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
163 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
164 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
165 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
166 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
167 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
168 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
169 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
170 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
171 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
172 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
173 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
174 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
175 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
176 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
177 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
178 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
179 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
180 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
181 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
182 INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
183
184#define INTEL_HSW_M_IDS(info) \
185 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
186 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
187 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
188 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
189 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
190 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
191 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
192 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
193 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
194 INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
195 INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
196 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
197 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
199 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
200
201#define INTEL_VLV_M_IDS(info) \
202 INTEL_VGA_DEVICE(0x0f30, info), \
203 INTEL_VGA_DEVICE(0x0f31, info), \
204 INTEL_VGA_DEVICE(0x0f32, info), \
205 INTEL_VGA_DEVICE(0x0f33, info), \
206 INTEL_VGA_DEVICE(0x0157, info)
207
208#define INTEL_VLV_D_IDS(info) \
209 INTEL_VGA_DEVICE(0x0155, info)
210
211#endif /* _I915_PCIIDS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-12 04:02:03 -0400