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authorJani Nikula <jani.nikula@intel.com>2015-02-25 07:46:53 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-03-10 04:59:32 -0400
commit0e71244c1bb873f0e3be3b79d3436d7ef2601029 (patch)
tree35ee79262d5284038745bf6417daa7553a4b5ed9 /include/drm
parentbd5da992b96bc018c3e64ffc5ac15cbe301f6440 (diff)
drm/dp: add DPCD definitions from eDP 1.2
Mostly display control related DPCD addresses. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/drm_dp_helper.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 98fefe45d158..a3ecaa06c9db 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -341,6 +341,38 @@
341 341
342#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 342#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
343 343
344#define DP_EDP_GENERAL_CAP_1 0x701
345
346#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
347
348#define DP_EDP_GENERAL_CAP_2 0x703
349
350#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
351
352#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
353
354#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
355#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
356
357#define DP_EDP_PWMGEN_BIT_COUNT 0x724
358#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
359#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
360
361#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
362
363#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
364
365#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
366#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
367#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
368
369#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
370#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
371#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
372
373#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
374#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
375
344#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 376#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
345#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 377#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
346#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 378#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */