diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
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committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /include/drm/drm_dp_helper.h | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'include/drm/drm_dp_helper.h')
-rw-r--r-- | include/drm/drm_dp_helper.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index a49e791db0b0..91567bbdb027 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h | |||
@@ -23,6 +23,9 @@ | |||
23 | #ifndef _DRM_DP_HELPER_H_ | 23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ | 24 | #define _DRM_DP_HELPER_H_ |
25 | 25 | ||
26 | #include <linux/types.h> | ||
27 | #include <linux/i2c.h> | ||
28 | |||
26 | /* From the VESA DisplayPort spec */ | 29 | /* From the VESA DisplayPort spec */ |
27 | 30 | ||
28 | #define AUX_NATIVE_WRITE 0x8 | 31 | #define AUX_NATIVE_WRITE 0x8 |
@@ -50,6 +53,7 @@ | |||
50 | 53 | ||
51 | #define DP_MAX_LANE_COUNT 0x002 | 54 | #define DP_MAX_LANE_COUNT 0x002 |
52 | # define DP_MAX_LANE_COUNT_MASK 0x1f | 55 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
56 | # define DP_TPS3_SUPPORTED (1 << 6) | ||
53 | # define DP_ENHANCED_FRAME_CAP (1 << 7) | 57 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
54 | 58 | ||
55 | #define DP_MAX_DOWNSPREAD 0x003 | 59 | #define DP_MAX_DOWNSPREAD 0x003 |
@@ -68,10 +72,13 @@ | |||
68 | 72 | ||
69 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 | 73 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
70 | 74 | ||
75 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e | ||
76 | |||
71 | /* link configuration */ | 77 | /* link configuration */ |
72 | #define DP_LINK_BW_SET 0x100 | 78 | #define DP_LINK_BW_SET 0x100 |
73 | # define DP_LINK_BW_1_62 0x06 | 79 | # define DP_LINK_BW_1_62 0x06 |
74 | # define DP_LINK_BW_2_7 0x0a | 80 | # define DP_LINK_BW_2_7 0x0a |
81 | # define DP_LINK_BW_5_4 0x14 | ||
75 | 82 | ||
76 | #define DP_LANE_COUNT_SET 0x101 | 83 | #define DP_LANE_COUNT_SET 0x101 |
77 | # define DP_LANE_COUNT_MASK 0x0f | 84 | # define DP_LANE_COUNT_MASK 0x0f |
@@ -81,6 +88,7 @@ | |||
81 | # define DP_TRAINING_PATTERN_DISABLE 0 | 88 | # define DP_TRAINING_PATTERN_DISABLE 0 |
82 | # define DP_TRAINING_PATTERN_1 1 | 89 | # define DP_TRAINING_PATTERN_1 1 |
83 | # define DP_TRAINING_PATTERN_2 2 | 90 | # define DP_TRAINING_PATTERN_2 2 |
91 | # define DP_TRAINING_PATTERN_3 3 | ||
84 | # define DP_TRAINING_PATTERN_MASK 0x3 | 92 | # define DP_TRAINING_PATTERN_MASK 0x3 |
85 | 93 | ||
86 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) | 94 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |