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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-26 16:07:55 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-26 16:07:55 -0400
commitb278240839e20fa9384ea430df463b367b90e04e (patch)
treef99f0c8cdd4cc7f177cd75440e6bd181cded7fb3 /include/asm-x86_64/smp.h
parentdd77a4ee0f3981693d4229aa1d57cea9e526ff47 (diff)
parent3f75f42d7733e73aca5c78326489efd4189e0111 (diff)
Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6
* 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6: (225 commits) [PATCH] Don't set calgary iommu as default y [PATCH] i386/x86-64: New Intel feature flags [PATCH] x86: Add a cumulative thermal throttle event counter. [PATCH] i386: Make the jiffies compares use the 64bit safe macros. [PATCH] x86: Refactor thermal throttle processing [PATCH] Add 64bit jiffies compares (for use with get_jiffies_64) [PATCH] Fix unwinder warning in traps.c [PATCH] x86: Allow disabling early pci scans with pci=noearly or disallowing conf1 [PATCH] x86: Move direct PCI scanning functions out of line [PATCH] i386/x86-64: Make all early PCI scans dependent on CONFIG_PCI [PATCH] Don't leak NT bit into next task [PATCH] i386/x86-64: Work around gcc bug with noreturn functions in unwinder [PATCH] Fix some broken white space in ia32_signal.c [PATCH] Initialize argument registers for 32bit signal handlers. [PATCH] Remove all traces of signal number conversion [PATCH] Don't synchronize time reading on single core AMD systems [PATCH] Remove outdated comment in x86-64 mmconfig code [PATCH] Use string instructions for Core2 copy/clear [PATCH] x86: - restore i8259A eoi status on resume [PATCH] i386: Split multi-line printk in oops output. ...
Diffstat (limited to 'include/asm-x86_64/smp.h')
-rw-r--r--include/asm-x86_64/smp.h29
1 files changed, 8 insertions, 21 deletions
diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h
index ce97f65e1d10..d6b7c057edba 100644
--- a/include/asm-x86_64/smp.h
+++ b/include/asm-x86_64/smp.h
@@ -4,27 +4,18 @@
4/* 4/*
5 * We need the APIC definitions automatically as part of 'smp.h' 5 * We need the APIC definitions automatically as part of 'smp.h'
6 */ 6 */
7#ifndef __ASSEMBLY__
8#include <linux/threads.h> 7#include <linux/threads.h>
9#include <linux/cpumask.h> 8#include <linux/cpumask.h>
10#include <linux/bitops.h> 9#include <linux/bitops.h>
11extern int disable_apic; 10extern int disable_apic;
12#endif
13 11
14#ifdef CONFIG_X86_LOCAL_APIC
15#ifndef __ASSEMBLY__
16#include <asm/fixmap.h> 12#include <asm/fixmap.h>
17#include <asm/mpspec.h> 13#include <asm/mpspec.h>
18#ifdef CONFIG_X86_IO_APIC
19#include <asm/io_apic.h> 14#include <asm/io_apic.h>
20#endif
21#include <asm/apic.h> 15#include <asm/apic.h>
22#include <asm/thread_info.h> 16#include <asm/thread_info.h>
23#endif
24#endif
25 17
26#ifdef CONFIG_SMP 18#ifdef CONFIG_SMP
27#ifndef ASSEMBLY
28 19
29#include <asm/pda.h> 20#include <asm/pda.h>
30 21
@@ -42,7 +33,6 @@ extern cpumask_t cpu_initialized;
42 33
43extern void smp_alloc_memory(void); 34extern void smp_alloc_memory(void);
44extern volatile unsigned long smp_invalidate_needed; 35extern volatile unsigned long smp_invalidate_needed;
45extern int pic_mode;
46extern void lock_ipi_call_lock(void); 36extern void lock_ipi_call_lock(void);
47extern void unlock_ipi_call_lock(void); 37extern void unlock_ipi_call_lock(void);
48extern int smp_num_siblings; 38extern int smp_num_siblings;
@@ -74,20 +64,16 @@ static inline int hard_smp_processor_id(void)
74 return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID)); 64 return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
75} 65}
76 66
77extern int safe_smp_processor_id(void);
78extern int __cpu_disable(void); 67extern int __cpu_disable(void);
79extern void __cpu_die(unsigned int cpu); 68extern void __cpu_die(unsigned int cpu);
80extern void prefill_possible_map(void); 69extern void prefill_possible_map(void);
81extern unsigned num_processors; 70extern unsigned num_processors;
82extern unsigned disabled_cpus; 71extern unsigned disabled_cpus;
83 72
84#endif /* !ASSEMBLY */
85
86#define NO_PROC_ID 0xFF /* No processor magic marker */ 73#define NO_PROC_ID 0xFF /* No processor magic marker */
87 74
88#endif 75#endif
89 76
90#ifndef ASSEMBLY
91/* 77/*
92 * Some lowlevel functions might want to know about 78 * Some lowlevel functions might want to know about
93 * the real APIC ID <-> CPU # mapping. 79 * the real APIC ID <-> CPU # mapping.
@@ -109,11 +95,8 @@ static inline int cpu_present_to_apicid(int mps_cpu)
109 return BAD_APICID; 95 return BAD_APICID;
110} 96}
111 97
112#endif /* !ASSEMBLY */
113
114#ifndef CONFIG_SMP 98#ifndef CONFIG_SMP
115#define stack_smp_processor_id() 0 99#define stack_smp_processor_id() 0
116#define safe_smp_processor_id() 0
117#define cpu_logical_map(x) (x) 100#define cpu_logical_map(x) (x)
118#else 101#else
119#include <asm/thread_info.h> 102#include <asm/thread_info.h>
@@ -125,19 +108,23 @@ static inline int cpu_present_to_apicid(int mps_cpu)
125}) 108})
126#endif 109#endif
127 110
128#ifndef __ASSEMBLY__
129static __inline int logical_smp_processor_id(void) 111static __inline int logical_smp_processor_id(void)
130{ 112{
131 /* we don't want to mark this access volatile - bad code generation */ 113 /* we don't want to mark this access volatile - bad code generation */
132 return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR)); 114 return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
133} 115}
134#endif
135 116
136#ifdef CONFIG_SMP 117#ifdef CONFIG_SMP
137#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu] 118#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu]
138#else 119#else
139#define cpu_physical_id(cpu) boot_cpu_id 120#define cpu_physical_id(cpu) boot_cpu_id
140#endif 121static inline int smp_call_function_single(int cpuid, void (*func) (void *info),
141 122 void *info, int retry, int wait)
123{
124 /* Disable interrupts here? */
125 func(info);
126 return 0;
127}
128#endif /* !CONFIG_SMP */
142#endif 129#endif
143 130