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authorRusty Russell <rusty@rustcorp.com.au>2007-07-17 09:37:17 -0400
committerAvi Kivity <avi@qumranet.com>2007-10-13 04:18:19 -0400
commit7075bc816cfad142da92207ed5a6f3da55b143ef (patch)
treed7b7581a9968d89fac5587d2378390b5939d28ec /include/asm-x86
parent8fc0d085f521a2a76418f8f569cf1cd27f0e43d4 (diff)
KVM: Use standard CR8 flags, and fix TPR definition
Intel manual (and KVM definition) say the TPR is 4 bits wide. Also fix CR8_RESEVED_BITS typo. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/processor-flags.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-x86/processor-flags.h b/include/asm-x86/processor-flags.h
index 5404e90edd57..199cab107d85 100644
--- a/include/asm-x86/processor-flags.h
+++ b/include/asm-x86/processor-flags.h
@@ -63,7 +63,7 @@
63/* 63/*
64 * x86-64 Task Priority Register, CR8 64 * x86-64 Task Priority Register, CR8
65 */ 65 */
66#define X86_CR8_TPR 0x00000007 /* task priority register */ 66#define X86_CR8_TPR 0x0000000F /* task priority register */
67 67
68/* 68/*
69 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> 69 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>