Merge branch 'linus' into x86/x2apic

Conflicts:
	arch/x86/kernel/cpu/cyrix.c
	include/asm-x86/cpufeature.h

Signed-off-by: Ingo Molnar <mingo@elte.hu>

22 files changed, 82 insertions, 46 deletions

diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
index 22aa58ca1991..dcc812067394 100644
--- a/include/asm-x86/amd_iommu_types.h
+++ b/include/asm-x86/amd_iommu_types.h
@@ -31,9 +31,6 @@
 #define ALIAS_TABLE_ENTRY_SIZE          2
 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
 
-/* helper macros */
-#define LOW_U32(x) ((x) & ((1ULL << 32)-1))
-
 /* Length of the MMIO region for the AMD IOMMU */
 #define MMIO_REGION_LENGTH       0x4000
 
@@ -69,6 +66,9 @@
 #define MMIO_EVT_TAIL_OFFSET    0x2018
 #define MMIO_STATUS_OFFSET      0x2020
 
+/* MMIO status bits */
+#define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
+
 /* feature control bits */
 #define CONTROL_IOMMU_EN        0x00ULL
 #define CONTROL_HT_TUN_EN       0x01ULL
@@ -89,6 +89,7 @@
 #define CMD_INV_IOMMU_PAGES     0x03
 
 #define CMD_COMPL_WAIT_STORE_MASK       0x01
+#define CMD_COMPL_WAIT_INT_MASK         0x02
 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 
@@ -99,6 +100,7 @@
 #define DEV_ENTRY_TRANSLATION   0x01
 #define DEV_ENTRY_IR            0x3d
 #define DEV_ENTRY_IW            0x3e
+#define DEV_ENTRY_NO_PAGE_FAULT 0x62
 #define DEV_ENTRY_EX            0x67
 #define DEV_ENTRY_SYSMGT1       0x68
 #define DEV_ENTRY_SYSMGT2       0x69
diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h
index a0095191c02e..91c7d03e65bc 100644
--- a/include/asm-x86/atomic_64.h
+++ b/include/asm-x86/atomic_64.h
@@ -228,7 +228,7 @@ static inline void atomic64_add(long i, atomic64_t *v)
 {
         asm volatile(LOCK_PREFIX "addq %1,%0"
                      : "=m" (v->counter)
-                     : "ir" (i), "m" (v->counter));
+                     : "er" (i), "m" (v->counter));
 }
 
 /**
@@ -242,7 +242,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
 {
         asm volatile(LOCK_PREFIX "subq %1,%0"
                      : "=m" (v->counter)
-                     : "ir" (i), "m" (v->counter));
+                     : "er" (i), "m" (v->counter));
 }
 
 /**
@@ -260,7 +260,7 @@ static inline int atomic64_sub_and_test(long i, atomic64_t *v)
 
         asm volatile(LOCK_PREFIX "subq %2,%0; sete %1"
                      : "=m" (v->counter), "=qm" (c)
-                     : "ir" (i), "m" (v->counter) : "memory");
+                     : "er" (i), "m" (v->counter) : "memory");
         return c;
 }
 
@@ -341,7 +341,7 @@ static inline int atomic64_add_negative(long i, atomic64_t *v)
 
         asm volatile(LOCK_PREFIX "addq %2,%0; sets %1"
                      : "=m" (v->counter), "=qm" (c)
-                     : "ir" (i), "m" (v->counter) : "memory");
+                     : "er" (i), "m" (v->counter) : "memory");
         return c;
 }
 
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 8d842af4cf7a..c6845b94be84 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -93,6 +93,7 @@
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_2      (4*32+20) /* Streaming SIMD Extensions-4.2 */
 #define X86_FEATURE_X2APIC      (4*32+21) /* x2APIC */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
@@ -192,6 +193,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_gbpages         boot_cpu_has(X86_FEATURE_GBPAGES)
 #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 #define cpu_has_pat             boot_cpu_has(X86_FEATURE_PAT)
+#define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
 #define cpu_has_x2apic          boot_cpu_has(X86_FEATURE_X2APIC)
 
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
diff --git a/include/asm-x86/genapic_32.h b/include/asm-x86/genapic_32.h
index b02ea6e17de8..754d635f90ff 100644
--- a/include/asm-x86/genapic_32.h
+++ b/include/asm-x86/genapic_32.h
@@ -118,6 +118,7 @@ enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
 #define get_uv_system_type()            UV_NONE
 #define is_uv_system()                  0
 #define uv_wakeup_secondary(a, b)       1
+#define uv_system_init()                do {} while (0)
 
 
 #endif
diff --git a/include/asm-x86/genapic_64.h b/include/asm-x86/genapic_64.h
index 1e832e49f54e..2e28a2bd5d95 100644
--- a/include/asm-x86/genapic_64.h
+++ b/include/asm-x86/genapic_64.h
@@ -50,6 +50,7 @@ extern int is_uv_system(void);
 extern struct genapic apic_x2apic_uv_x;
 DECLARE_PER_CPU(int, x2apic_extra_bits);
 extern void uv_cpu_init(void);
+extern void uv_system_init(void);
 extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip);
 
 extern void setup_apic_routing(void);
diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h
index bb06027fc83e..2c1cda0b8a86 100644
--- a/include/asm-x86/geode.h
+++ b/include/asm-x86/geode.h
@@ -50,6 +50,7 @@ extern int geode_get_dev_base(unsigned int dev);
 #define MSR_PIC_YSEL_HIGH       0x51400021
 #define MSR_PIC_ZSEL_LOW        0x51400022
 #define MSR_PIC_ZSEL_HIGH       0x51400023
+#define MSR_PIC_IRQM_LPC        0x51400025
 
 #define MSR_MFGPT_IRQ           0x51400028
 #define MSR_MFGPT_NR            0x51400029
@@ -237,7 +238,7 @@ static inline u16 geode_mfgpt_read(int timer, u16 reg)
 }
 
 extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
-extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable);
+extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable);
 extern int geode_mfgpt_alloc_timer(int timer, int domain);
 
 #define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index 6d3b21063419..56d00e31aec0 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -63,8 +63,6 @@ static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
 #else
                      : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
 #endif
-        if (unlikely(err))
-                init_fpu(current);
         return err;
 }
 
diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h
index bf5d629b3a39..0f954dc89cb3 100644
--- a/include/asm-x86/io.h
+++ b/include/asm-x86/io.h
@@ -21,7 +21,7 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
 
 #define build_mmio_read(name, size, type, reg, barrier) \
 static inline type name(const volatile void __iomem *addr) \
-{ type ret; asm volatile("mov" size " %1,%0":"=" reg (ret) \
+{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
 :"m" (*(volatile type __force *)addr) barrier); return ret; }
 
 #define build_mmio_write(name, size, type, reg, barrier) \
@@ -29,13 +29,13 @@ static inline void name(type val, volatile void __iomem *addr) \
 { asm volatile("mov" size " %0,%1": :reg (val), \
 "m" (*(volatile type __force *)addr) barrier); }
 
-build_mmio_read(readb, "b", unsigned char, "q", :"memory")
-build_mmio_read(readw, "w", unsigned short, "r", :"memory")
-build_mmio_read(readl, "l", unsigned int, "r", :"memory")
+build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
+build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
+build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
 
-build_mmio_read(__readb, "b", unsigned char, "q", )
-build_mmio_read(__readw, "w", unsigned short, "r", )
-build_mmio_read(__readl, "l", unsigned int, "r", )
+build_mmio_read(__readb, "b", unsigned char, "=q", )
+build_mmio_read(__readw, "w", unsigned short, "=r", )
+build_mmio_read(__readl, "l", unsigned int, "=r", )
 
 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
@@ -59,8 +59,8 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
 #define mmiowb() barrier()
 
 #ifdef CONFIG_X86_64
-build_mmio_read(readq, "q", unsigned long, "r", :"memory")
-build_mmio_read(__readq, "q", unsigned long, "r", )
+build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
+build_mmio_read(__readq, "q", unsigned long, "=r", )
 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
 build_mmio_write(__writeq, "q", unsigned long, "r", )
 
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
index b95d167b7fb2..a48c7f2dbdc0 100644
--- a/include/asm-x86/irq_vectors.h
+++ b/include/asm-x86/irq_vectors.h
@@ -76,6 +76,7 @@
 #define CALL_FUNCTION_SINGLE_VECTOR     0xfb
 #define THERMAL_APIC_VECTOR             0xfa
 #define THRESHOLD_APIC_VECTOR           0xf9
+#define UV_BAU_MESSAGE                  0xf8
 #define INVALIDATE_TLB_VECTOR_END       0xf7
 #define INVALIDATE_TLB_VECTOR_START     0xf0    /* f0-f7 used for TLB flush */
 
diff --git a/include/asm-x86/kexec.h b/include/asm-x86/kexec.h
index c0e52a14fd4d..4246ab7dc988 100644
--- a/include/asm-x86/kexec.h
+++ b/include/asm-x86/kexec.h
@@ -41,6 +41,10 @@
 # define PAGES_NR               17
 #endif
 
+#ifdef CONFIG_X86_32
+# define KEXEC_CONTROL_CODE_MAX_SIZE    2048
+#endif
+
 #ifndef __ASSEMBLY__
 
 #include <linux/string.h>
@@ -63,7 +67,7 @@
 /* Maximum address we can use for the control code buffer */
 # define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
 
-# define KEXEC_CONTROL_CODE_SIZE        4096
+# define KEXEC_CONTROL_PAGE_SIZE        4096
 
 /* The native architecture */
 # define KEXEC_ARCH KEXEC_ARCH_386
@@ -79,7 +83,7 @@
 # define KEXEC_CONTROL_MEMORY_LIMIT     (0xFFFFFFFFFFUL)
 
 /* Allocate one page for the pdp and the second for the code */
-# define KEXEC_CONTROL_CODE_SIZE  (4096UL + 4096UL)
+# define KEXEC_CONTROL_PAGE_SIZE  (4096UL + 4096UL)
 
 /* The native architecture */
 # define KEXEC_ARCH KEXEC_ARCH_X86_64
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 0f3c53114614..c2e34c275900 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -722,7 +722,7 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
 
 #define __kvm_handle_fault_on_reboot(insn) \
         "666: " insn "\n\t" \
-        ".pushsection .text.fixup, \"ax\" \n" \
+        ".pushsection .fixup, \"ax\" \n" \
         "667: \n\t" \
         KVM_EX_PUSH " $666b \n\t" \
         "jmp kvm_handle_fault_on_reboot \n\t" \
diff --git a/include/asm-x86/mce.h b/include/asm-x86/mce.h
index 94f1fd79e22a..531eaa587455 100644
--- a/include/asm-x86/mce.h
+++ b/include/asm-x86/mce.h
@@ -92,6 +92,7 @@ extern int mce_disabled;
 
 void mce_log(struct mce *m);
 DECLARE_PER_CPU(struct sys_device, device_mce);
+extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 
 #ifdef CONFIG_X86_MCE_INTEL
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
diff --git a/include/asm-x86/mman.h b/include/asm-x86/mman.h
index c1682b542daf..90bc4108a4fd 100644
--- a/include/asm-x86/mman.h
+++ b/include/asm-x86/mman.h
@@ -12,6 +12,7 @@
 #define MAP_NORESERVE   0x4000          /* don't check for reservations */
 #define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
 #define MAP_NONBLOCK    0x10000         /* do not block on IO */
+#define MAP_STACK       0x20000         /* give out an address that is best suited for process/thread stacks */
 
 #define MCL_CURRENT     1               /* lock all current mappings */
 #define MCL_FUTURE      2               /* lock all future mappings */
diff --git a/include/asm-x86/mmconfig.h b/include/asm-x86/mmconfig.h
index 95beda07c6fa..e293ab81e850 100644
--- a/include/asm-x86/mmconfig.h
+++ b/include/asm-x86/mmconfig.h
@@ -3,7 +3,7 @@
 
 #ifdef CONFIG_PCI_MMCONFIG
 extern void __cpuinit fam10h_check_enable_mmcfg(void);
-extern void __init check_enable_amd_mmconf_dmi(void);
+extern void __cpuinit check_enable_amd_mmconf_dmi(void);
 #else
 static inline void fam10h_check_enable_mmcfg(void) { }
 static inline void check_enable_amd_mmconf_dmi(void) { }
diff --git a/include/asm-x86/mmzone_32.h b/include/asm-x86/mmzone_32.h
index b2298a227567..5862e6460658 100644
--- a/include/asm-x86/mmzone_32.h
+++ b/include/asm-x86/mmzone_32.h
@@ -97,10 +97,16 @@ static inline int pfn_valid(int pfn)
         reserve_bootmem_node(NODE_DATA(0), (addr), (size), (flags))
 #define alloc_bootmem(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_nopanic(x) \
+        __alloc_bootmem_node_nopanic(NODE_DATA(0), (x), SMP_CACHE_BYTES, \
+                                __pa(MAX_DMA_ADDRESS))
 #define alloc_bootmem_low(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
 #define alloc_bootmem_pages(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_pages_nopanic(x) \
+        __alloc_bootmem_node_nopanic(NODE_DATA(0), (x), PAGE_SIZE, \
+                                __pa(MAX_DMA_ADDRESS))
 #define alloc_bootmem_low_pages(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
 #define alloc_bootmem_node(pgdat, x)                                    \
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index ca110ee73f07..2362cfda1fbc 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -52,14 +52,14 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
 {
         DECLARE_ARGS(val, low, high);
 
-        asm volatile("2: rdmsr ; xor %0,%0\n"
+        asm volatile("2: rdmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %3,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=r" (*err), EAX_EDX_RET(val, low, high)
-                     : "c" (msr), "i" (-EFAULT));
+                     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
+                     : "c" (msr), [fault] "i" (-EFAULT));
         return EAX_EDX_VAL(val, low, high);
 }
 
@@ -73,15 +73,15 @@ static inline int native_write_msr_safe(unsigned int msr,
                                         unsigned low, unsigned high)
 {
         int err;
-        asm volatile("2: wrmsr ; xor %0,%0\n"
+        asm volatile("2: wrmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %4,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=a" (err)
+                     : [err] "=a" (err)
                      : "c" (msr), "0" (low), "d" (high),
-                       "i" (-EFAULT)
+                       [fault] "i" (-EFAULT)
                      : "memory");
         return err;
 }
@@ -192,19 +192,20 @@ do {                                                            \
 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
 
 #ifdef CONFIG_SMP
-void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-
 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 #else  /*  CONFIG_SMP  */
-static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
         rdmsr(msr_no, *l, *h);
+        return 0;
 }
-static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
         wrmsr(msr_no, l, h);
+        return 0;
 }
 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
                                     u32 *l, u32 *h)
diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h
index 4e91ee1e37aa..f643a3a92da0 100644
--- a/include/asm-x86/percpu.h
+++ b/include/asm-x86/percpu.h
@@ -182,7 +182,7 @@ do {							\
         DEFINE_PER_CPU(_type, _name) = _initvalue;                      \
         __typeof__(_type) _name##_early_map[NR_CPUS] __initdata =       \
                                 { [0 ... NR_CPUS-1] = _initvalue };     \
-        __typeof__(_type) *_name##_early_ptr = _name##_early_map
+        __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
 
 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name)                      \
         EXPORT_PER_CPU_SYMBOL(_name)
diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
index ac5fff4cc58a..549144d03d99 100644
--- a/include/asm-x86/pgtable_64.h
+++ b/include/asm-x86/pgtable_64.h
@@ -151,7 +151,7 @@ static inline void native_pgd_clear(pgd_t *pgd)
 #define VMALLOC_END      _AC(0xffffe1ffffffffff, UL)
 #define VMEMMAP_START    _AC(0xffffe20000000000, UL)
 #define MODULES_VADDR    _AC(0xffffffffa0000000, UL)
-#define MODULES_END      _AC(0xfffffffffff00000, UL)
+#define MODULES_END      _AC(0xffffffffff000000, UL)
 #define MODULES_LEN   (MODULES_END - MODULES_VADDR)
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 79338fe965d2..d2bf5fe8f4ff 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -729,6 +729,29 @@ extern unsigned long		boot_option_idle_override;
 extern unsigned long            idle_halt;
 extern unsigned long            idle_nomwait;
 
+/*
+ * on systems with caches, caches must be flashed as the absolute
+ * last instruction before going into a suspended halt.  Otherwise,
+ * dirty data can linger in the cache and become stale on resume,
+ * leading to strange errors.
+ *
+ * perform a variety of operations to guarantee that the compiler
+ * will not reorder instructions.  wbinvd itself is serializing
+ * so the processor will not reorder.
+ *
+ * Systems without cache can just go into halt.
+ */
+static inline void wbinvd_halt(void)
+{
+        mb();
+        /* check for clflush to determine if wbinvd is legal */
+        if (cpu_has_clflush)
+                asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
+        else
+                while (1)
+                        halt();
+}
+
 extern void enable_sep_cpu(void);
 extern int sysenter_setup(void);
 
diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h
index 4f9a9861799a..e39c790dbfd2 100644
--- a/include/asm-x86/spinlock.h
+++ b/include/asm-x86/spinlock.h
@@ -65,7 +65,7 @@ static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->slock);
 
-        return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
+        return (((tmp >> 8) - tmp) & 0xff) > 1;
 }
 
 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
@@ -127,7 +127,7 @@ static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->slock);
 
-        return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
+        return (((tmp >> 16) - tmp) & 0xffff) > 1;
 }
 
 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
diff --git a/include/asm-x86/uv/uv_bau.h b/include/asm-x86/uv/uv_bau.h
index 91ac0dfb7588..610b6b308e93 100644
--- a/include/asm-x86/uv/uv_bau.h
+++ b/include/asm-x86/uv/uv_bau.h
@@ -40,11 +40,6 @@
 #define UV_ACTIVATION_DESCRIPTOR_SIZE   32
 #define UV_DISTRIBUTION_SIZE            256
 #define UV_SW_ACK_NPENDING              8
-#define UV_BAU_MESSAGE                  200
-/*
- * Messaging irq; see irq_64.h and include/asm-x86/hw_irq_64.h
- * To be dynamically allocated in the future
- */
 #define UV_NET_ENDPOINT_INTD            0x38
 #define UV_DESC_BASE_PNODE_SHIFT        49
 #define UV_PAYLOADQ_PNODE_SHIFT         49
diff --git a/include/asm-x86/xen/hypervisor.h b/include/asm-x86/xen/hypervisor.h
index 8e15dd28c91f..04ee0610014a 100644
--- a/include/asm-x86/xen/hypervisor.h
+++ b/include/asm-x86/xen/hypervisor.h
@@ -35,7 +35,6 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
-#include <linux/version.h>
 
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>