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authorMark Langsdorf <mark.langsdorf@amd.com>2008-08-14 10:11:26 -0400
committerIngo Molnar <mingo@elte.hu>2008-08-15 08:04:30 -0400
commit394a15051c33f2b18e72f42283b36a9388fa414b (patch)
tree3e0b4acbd9e940758b184991d78bfe8f3a168050 /include/asm-x86
parentdcc984166870150709f0c645b521a47becd9a047 (diff)
x86: invalidate caches before going into suspend
When a CPU core is shut down, all of its caches need to be flushed to prevent stale data from causing errors if the core is resumed. Current Linux suspend code performs an assignment after the flush, which can add dirty data back to the cache.  On some AMD platforms, additional speculative reads have caused crashes on resume because of this dirty data. Relocate the cache flush to be the very last thing done before halting.  Tie into an assembly line so the compile will not reorder it.  Add some documentation explaining what is going on and why we're doing this. Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Acked-by: Mark Borden <mark.borden@amd.com> Acked-by: Michael Hohmuth <michael.hohmuth@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/processor.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 5f58da401b43..4df3e2f6fb56 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -728,6 +728,29 @@ extern unsigned long boot_option_idle_override;
728extern unsigned long idle_halt; 728extern unsigned long idle_halt;
729extern unsigned long idle_nomwait; 729extern unsigned long idle_nomwait;
730 730
731/*
732 * on systems with caches, caches must be flashed as the absolute
733 * last instruction before going into a suspended halt. Otherwise,
734 * dirty data can linger in the cache and become stale on resume,
735 * leading to strange errors.
736 *
737 * perform a variety of operations to guarantee that the compiler
738 * will not reorder instructions. wbinvd itself is serializing
739 * so the processor will not reorder.
740 *
741 * Systems without cache can just go into halt.
742 */
743static inline void wbinvd_halt(void)
744{
745 mb();
746 /* check for clflush to determine if wbinvd is legal */
747 if (cpu_has_clflush)
748 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
749 else
750 while (1)
751 halt();
752}
753
731extern void enable_sep_cpu(void); 754extern void enable_sep_cpu(void);
732extern int sysenter_setup(void); 755extern int sysenter_setup(void);
733 756