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authorYinghai Lu <Yinghai.Lu@Sun.COM>2008-02-19 06:21:20 -0500
committerIngo Molnar <mingo@elte.hu>2008-04-26 17:41:04 -0400
commit30a18d6c3f1e774de656ebd8ff219d53e2ba4029 (patch)
tree22aad98a32fc182736f78193938a24175a168b81 /include/asm-x86
parent35ddd068fb94b187e94a3fc497ccecf27bdda9ae (diff)
x86: multi pci root bus with different io resource range, on 64-bit
scan AMD opteron io/mmio routing to make sure every pci root bus get correct resource range. Thus later pci scan could assign correct resource to device with unassigned resource. this can fix a system without _CRS for multi pci root bus. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/topology.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 4793ae745a78..0e6d6b03affe 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -193,6 +193,9 @@ extern cpumask_t cpu_coregroup_map(int cpu);
193#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu)) 193#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
194#endif 194#endif
195 195
196struct pci_bus;
197void set_pci_bus_resources_arch_default(struct pci_bus *b);
198
196#ifdef CONFIG_SMP 199#ifdef CONFIG_SMP
197#define mc_capable() (boot_cpu_data.x86_max_cores > 1) 200#define mc_capable() (boot_cpu_data.x86_max_cores > 1)
198#define smt_capable() (smp_num_siblings > 1) 201#define smt_capable() (smp_num_siblings > 1)