diff options
| author | Jack Steiner <steiner@sgi.com> | 2008-05-28 10:51:18 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-06-02 06:56:00 -0400 |
| commit | 9f5314fb4d556d3132c784d0df47352b2830ca53 (patch) | |
| tree | c66945d21aab945f33498d8d146596b5d9e3a6e4 /include/asm-x86/uv/uv_mmrs.h | |
| parent | c46e62f73569d7ef42255bd6f31e35925b7f1492 (diff) | |
x86, uv: update macros used by UV platform
Update the UV address macros to better describe the
fields of UV physical addresses. Improve comments
in the header files. Add additional MMR definitions.
Signed-off-by: Jack Steiner <steiner@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/uv/uv_mmrs.h')
| -rw-r--r-- | include/asm-x86/uv/uv_mmrs.h | 509 |
1 files changed, 505 insertions, 4 deletions
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h index 3b69fe6b6376..ac9846076521 100644 --- a/include/asm-x86/uv/uv_mmrs.h +++ b/include/asm-x86/uv/uv_mmrs.h | |||
| @@ -11,11 +11,46 @@ | |||
| 11 | #ifndef __ASM_X86_UV_MMRS__ | 11 | #ifndef __ASM_X86_UV_MMRS__ |
| 12 | #define __ASM_X86_UV_MMRS__ | 12 | #define __ASM_X86_UV_MMRS__ |
| 13 | 13 | ||
| 14 | /* | 14 | #define UV_MMR_ENABLE (1UL << 63) |
| 15 | * AUTO GENERATED - Do not edit | ||
| 16 | */ | ||
| 17 | 15 | ||
| 18 | #define UV_MMR_ENABLE (1UL << 63) | 16 | /* ========================================================================= */ |
| 17 | /* UVH_BAU_DATA_CONFIG */ | ||
| 18 | /* ========================================================================= */ | ||
| 19 | #define UVH_BAU_DATA_CONFIG 0x61680UL | ||
| 20 | #define UVH_BAU_DATA_CONFIG_32 0x0450 | ||
| 21 | |||
| 22 | #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | ||
| 23 | #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 24 | #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 | ||
| 25 | #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 26 | #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | ||
| 27 | #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 28 | #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 | ||
| 29 | #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 30 | #define UVH_BAU_DATA_CONFIG_P_SHFT 13 | ||
| 31 | #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | ||
| 32 | #define UVH_BAU_DATA_CONFIG_T_SHFT 15 | ||
| 33 | #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | ||
| 34 | #define UVH_BAU_DATA_CONFIG_M_SHFT 16 | ||
| 35 | #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | ||
| 36 | #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | ||
| 37 | #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 38 | |||
| 39 | union uvh_bau_data_config_u { | ||
| 40 | unsigned long v; | ||
| 41 | struct uvh_bau_data_config_s { | ||
| 42 | unsigned long vector_ : 8; /* RW */ | ||
| 43 | unsigned long dm : 3; /* RW */ | ||
| 44 | unsigned long destmode : 1; /* RW */ | ||
| 45 | unsigned long status : 1; /* RO */ | ||
| 46 | unsigned long p : 1; /* RO */ | ||
| 47 | unsigned long rsvd_14 : 1; /* */ | ||
| 48 | unsigned long t : 1; /* RO */ | ||
| 49 | unsigned long m : 1; /* RW */ | ||
| 50 | unsigned long rsvd_17_31: 15; /* */ | ||
| 51 | unsigned long apic_id : 32; /* RW */ | ||
| 52 | } s; | ||
| 53 | }; | ||
| 19 | 54 | ||
| 20 | /* ========================================================================= */ | 55 | /* ========================================================================= */ |
| 21 | /* UVH_IPI_INT */ | 56 | /* UVH_IPI_INT */ |
| @@ -109,6 +144,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u { | |||
| 109 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ | 144 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ |
| 110 | /* ========================================================================= */ | 145 | /* ========================================================================= */ |
| 111 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL | 146 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL |
| 147 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0aa0 | ||
| 112 | 148 | ||
| 113 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | 149 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 |
| 114 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL | 150 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL |
| @@ -169,6 +205,7 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 169 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ | 205 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ |
| 170 | /* ========================================================================= */ | 206 | /* ========================================================================= */ |
| 171 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL | 207 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL |
| 208 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0aa8 | ||
| 172 | 209 | ||
| 173 | /* ========================================================================= */ | 210 | /* ========================================================================= */ |
| 174 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ | 211 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ |
| @@ -248,6 +285,331 @@ union uvh_lb_bau_sb_descriptor_base_u { | |||
| 248 | }; | 285 | }; |
| 249 | 286 | ||
| 250 | /* ========================================================================= */ | 287 | /* ========================================================================= */ |
| 288 | /* UVH_LB_MCAST_AOERR0_RPT_ENABLE */ | ||
| 289 | /* ========================================================================= */ | ||
| 290 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL | ||
| 291 | |||
| 292 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0 | ||
| 293 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL | ||
| 294 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1 | ||
| 295 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL | ||
| 296 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2 | ||
| 297 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL | ||
| 298 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3 | ||
| 299 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL | ||
| 300 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4 | ||
| 301 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL | ||
| 302 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5 | ||
| 303 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL | ||
| 304 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6 | ||
| 305 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL | ||
| 306 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7 | ||
| 307 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL | ||
| 308 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8 | ||
| 309 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL | ||
| 310 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9 | ||
| 311 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL | ||
| 312 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10 | ||
| 313 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL | ||
| 314 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11 | ||
| 315 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL | ||
| 316 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12 | ||
| 317 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL | ||
| 318 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13 | ||
| 319 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL | ||
| 320 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14 | ||
| 321 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL | ||
| 322 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15 | ||
| 323 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL | ||
| 324 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16 | ||
| 325 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL | ||
| 326 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17 | ||
| 327 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL | ||
| 328 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18 | ||
| 329 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL | ||
| 330 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19 | ||
| 331 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL | ||
| 332 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20 | ||
| 333 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL | ||
| 334 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21 | ||
| 335 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL | ||
| 336 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_SHFT 22 | ||
| 337 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_MASK 0x0000000000400000UL | ||
| 338 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 23 | ||
| 339 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000000800000UL | ||
| 340 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 24 | ||
| 341 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000001000000UL | ||
| 342 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 25 | ||
| 343 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000002000000UL | ||
| 344 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 26 | ||
| 345 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000004000000UL | ||
| 346 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 27 | ||
| 347 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000008000000UL | ||
| 348 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 28 | ||
| 349 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000010000000UL | ||
| 350 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 29 | ||
| 351 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000020000000UL | ||
| 352 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 30 | ||
| 353 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000040000000UL | ||
| 354 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 31 | ||
| 355 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000080000000UL | ||
| 356 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 32 | ||
| 357 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000100000000UL | ||
| 358 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 33 | ||
| 359 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000200000000UL | ||
| 360 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 34 | ||
| 361 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000400000000UL | ||
| 362 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 35 | ||
| 363 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000000800000000UL | ||
| 364 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 36 | ||
| 365 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000001000000000UL | ||
| 366 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 37 | ||
| 367 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000002000000000UL | ||
| 368 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 38 | ||
| 369 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000004000000000UL | ||
| 370 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 39 | ||
| 371 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000008000000000UL | ||
| 372 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 40 | ||
| 373 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000010000000000UL | ||
| 374 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 41 | ||
| 375 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000020000000000UL | ||
| 376 | |||
| 377 | union uvh_lb_mcast_aoerr0_rpt_enable_u { | ||
| 378 | unsigned long v; | ||
| 379 | struct uvh_lb_mcast_aoerr0_rpt_enable_s { | ||
| 380 | unsigned long mcast_obese_msg : 1; /* RW */ | ||
| 381 | unsigned long mcast_data_sb_err : 1; /* RW */ | ||
| 382 | unsigned long mcast_nack_buff_parity : 1; /* RW */ | ||
| 383 | unsigned long mcast_timeout : 1; /* RW */ | ||
| 384 | unsigned long mcast_inactive_reply : 1; /* RW */ | ||
| 385 | unsigned long mcast_upgrade_error : 1; /* RW */ | ||
| 386 | unsigned long mcast_reg_count_underflow : 1; /* RW */ | ||
| 387 | unsigned long mcast_rep_obese_msg : 1; /* RW */ | ||
| 388 | unsigned long ucache_req_runt_msg : 1; /* RW */ | ||
| 389 | unsigned long ucache_req_obese_msg : 1; /* RW */ | ||
| 390 | unsigned long ucache_req_data_sb_err : 1; /* RW */ | ||
| 391 | unsigned long ucache_rep_runt_msg : 1; /* RW */ | ||
| 392 | unsigned long ucache_rep_obese_msg : 1; /* RW */ | ||
| 393 | unsigned long ucache_rep_data_sb_err : 1; /* RW */ | ||
| 394 | unsigned long ucache_rep_command_err : 1; /* RW */ | ||
| 395 | unsigned long ucache_pend_timeout : 1; /* RW */ | ||
| 396 | unsigned long macc_req_runt_msg : 1; /* RW */ | ||
| 397 | unsigned long macc_req_obese_msg : 1; /* RW */ | ||
| 398 | unsigned long macc_req_data_sb_err : 1; /* RW */ | ||
| 399 | unsigned long macc_rep_runt_msg : 1; /* RW */ | ||
| 400 | unsigned long macc_rep_obese_msg : 1; /* RW */ | ||
| 401 | unsigned long macc_rep_data_sb_err : 1; /* RW */ | ||
| 402 | unsigned long macc_timeout : 1; /* RW */ | ||
| 403 | unsigned long macc_spurious_event : 1; /* RW */ | ||
| 404 | unsigned long ioh_destination_table_parity : 1; /* RW */ | ||
| 405 | unsigned long get_had_error_reply : 1; /* RW */ | ||
| 406 | unsigned long get_timeout : 1; /* RW */ | ||
| 407 | unsigned long lock_manager_had_error_reply : 1; /* RW */ | ||
| 408 | unsigned long put_had_error_reply : 1; /* RW */ | ||
| 409 | unsigned long put_timeout : 1; /* RW */ | ||
| 410 | unsigned long sb_activation_overrun : 1; /* RW */ | ||
| 411 | unsigned long completed_gb_activation_had_error_reply : 1; /* RW */ | ||
| 412 | unsigned long completed_gb_activation_timeout : 1; /* RW */ | ||
| 413 | unsigned long descriptor_buffer_0_parity : 1; /* RW */ | ||
| 414 | unsigned long descriptor_buffer_1_parity : 1; /* RW */ | ||
| 415 | unsigned long socket_destination_table_parity : 1; /* RW */ | ||
| 416 | unsigned long bau_reply_payload_corruption : 1; /* RW */ | ||
| 417 | unsigned long io_port_destination_table_parity : 1; /* RW */ | ||
| 418 | unsigned long intd_soft_ack_timeout : 1; /* RW */ | ||
| 419 | unsigned long int_rep_obese_msg : 1; /* RW */ | ||
| 420 | unsigned long int_rep_command_err : 1; /* RW */ | ||
| 421 | unsigned long int_timeout : 1; /* RW */ | ||
| 422 | unsigned long rsvd_42_63 : 22; /* */ | ||
| 423 | } s; | ||
| 424 | }; | ||
| 425 | |||
| 426 | /* ========================================================================= */ | ||
| 427 | /* UVH_LOCAL_INT0_CONFIG */ | ||
| 428 | /* ========================================================================= */ | ||
| 429 | #define UVH_LOCAL_INT0_CONFIG 0x61000UL | ||
| 430 | |||
| 431 | #define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 432 | #define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 433 | #define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8 | ||
| 434 | #define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 435 | #define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 436 | #define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 437 | #define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12 | ||
| 438 | #define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 439 | #define UVH_LOCAL_INT0_CONFIG_P_SHFT 13 | ||
| 440 | #define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 441 | #define UVH_LOCAL_INT0_CONFIG_T_SHFT 15 | ||
| 442 | #define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 443 | #define UVH_LOCAL_INT0_CONFIG_M_SHFT 16 | ||
| 444 | #define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 445 | #define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 446 | #define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 447 | |||
| 448 | union uvh_local_int0_config_u { | ||
| 449 | unsigned long v; | ||
| 450 | struct uvh_local_int0_config_s { | ||
| 451 | unsigned long vector_ : 8; /* RW */ | ||
| 452 | unsigned long dm : 3; /* RW */ | ||
| 453 | unsigned long destmode : 1; /* RW */ | ||
| 454 | unsigned long status : 1; /* RO */ | ||
| 455 | unsigned long p : 1; /* RO */ | ||
| 456 | unsigned long rsvd_14 : 1; /* */ | ||
| 457 | unsigned long t : 1; /* RO */ | ||
| 458 | unsigned long m : 1; /* RW */ | ||
| 459 | unsigned long rsvd_17_31: 15; /* */ | ||
| 460 | unsigned long apic_id : 32; /* RW */ | ||
| 461 | } s; | ||
| 462 | }; | ||
| 463 | |||
| 464 | /* ========================================================================= */ | ||
| 465 | /* UVH_LOCAL_INT0_ENABLE */ | ||
| 466 | /* ========================================================================= */ | ||
| 467 | #define UVH_LOCAL_INT0_ENABLE 0x65000UL | ||
| 468 | |||
| 469 | #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0 | ||
| 470 | #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL | ||
| 471 | #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1 | ||
| 472 | #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL | ||
| 473 | #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2 | ||
| 474 | #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL | ||
| 475 | #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3 | ||
| 476 | #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL | ||
| 477 | #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4 | ||
| 478 | #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL | ||
| 479 | #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5 | ||
| 480 | #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL | ||
| 481 | #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6 | ||
| 482 | #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL | ||
| 483 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7 | ||
| 484 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL | ||
| 485 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8 | ||
| 486 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL | ||
| 487 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9 | ||
| 488 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL | ||
| 489 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10 | ||
| 490 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL | ||
| 491 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11 | ||
| 492 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL | ||
| 493 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12 | ||
| 494 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL | ||
| 495 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13 | ||
| 496 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL | ||
| 497 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14 | ||
| 498 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL | ||
| 499 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15 | ||
| 500 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL | ||
| 501 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16 | ||
| 502 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL | ||
| 503 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17 | ||
| 504 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL | ||
| 505 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18 | ||
| 506 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL | ||
| 507 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19 | ||
| 508 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL | ||
| 509 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20 | ||
| 510 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL | ||
| 511 | #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21 | ||
| 512 | #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL | ||
| 513 | #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22 | ||
| 514 | #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL | ||
| 515 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23 | ||
| 516 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL | ||
| 517 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24 | ||
| 518 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL | ||
| 519 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25 | ||
| 520 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL | ||
| 521 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26 | ||
| 522 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL | ||
| 523 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27 | ||
| 524 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL | ||
| 525 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28 | ||
| 526 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL | ||
| 527 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29 | ||
| 528 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL | ||
| 529 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30 | ||
| 530 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL | ||
| 531 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31 | ||
| 532 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL | ||
| 533 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32 | ||
| 534 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL | ||
| 535 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33 | ||
| 536 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL | ||
| 537 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34 | ||
| 538 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL | ||
| 539 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35 | ||
| 540 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL | ||
| 541 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36 | ||
| 542 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL | ||
| 543 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37 | ||
| 544 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL | ||
| 545 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38 | ||
| 546 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL | ||
| 547 | #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39 | ||
| 548 | #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL | ||
| 549 | #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40 | ||
| 550 | #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL | ||
| 551 | #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41 | ||
| 552 | #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL | ||
| 553 | #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42 | ||
| 554 | #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL | ||
| 555 | #define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43 | ||
| 556 | #define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL | ||
| 557 | #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44 | ||
| 558 | #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL | ||
| 559 | |||
| 560 | union uvh_local_int0_enable_u { | ||
| 561 | unsigned long v; | ||
| 562 | struct uvh_local_int0_enable_s { | ||
| 563 | unsigned long lb_hcerr : 1; /* RW */ | ||
| 564 | unsigned long gr0_hcerr : 1; /* RW */ | ||
| 565 | unsigned long gr1_hcerr : 1; /* RW */ | ||
| 566 | unsigned long lh_hcerr : 1; /* RW */ | ||
| 567 | unsigned long rh_hcerr : 1; /* RW */ | ||
| 568 | unsigned long xn_hcerr : 1; /* RW */ | ||
| 569 | unsigned long si_hcerr : 1; /* RW */ | ||
| 570 | unsigned long lb_aoerr0 : 1; /* RW */ | ||
| 571 | unsigned long gr0_aoerr0 : 1; /* RW */ | ||
| 572 | unsigned long gr1_aoerr0 : 1; /* RW */ | ||
| 573 | unsigned long lh_aoerr0 : 1; /* RW */ | ||
| 574 | unsigned long rh_aoerr0 : 1; /* RW */ | ||
| 575 | unsigned long xn_aoerr0 : 1; /* RW */ | ||
| 576 | unsigned long si_aoerr0 : 1; /* RW */ | ||
| 577 | unsigned long lb_aoerr1 : 1; /* RW */ | ||
| 578 | unsigned long gr0_aoerr1 : 1; /* RW */ | ||
| 579 | unsigned long gr1_aoerr1 : 1; /* RW */ | ||
| 580 | unsigned long lh_aoerr1 : 1; /* RW */ | ||
| 581 | unsigned long rh_aoerr1 : 1; /* RW */ | ||
| 582 | unsigned long xn_aoerr1 : 1; /* RW */ | ||
| 583 | unsigned long si_aoerr1 : 1; /* RW */ | ||
| 584 | unsigned long rh_vpi_int : 1; /* RW */ | ||
| 585 | unsigned long system_shutdown_int : 1; /* RW */ | ||
| 586 | unsigned long lb_irq_int_0 : 1; /* RW */ | ||
| 587 | unsigned long lb_irq_int_1 : 1; /* RW */ | ||
| 588 | unsigned long lb_irq_int_2 : 1; /* RW */ | ||
| 589 | unsigned long lb_irq_int_3 : 1; /* RW */ | ||
| 590 | unsigned long lb_irq_int_4 : 1; /* RW */ | ||
| 591 | unsigned long lb_irq_int_5 : 1; /* RW */ | ||
| 592 | unsigned long lb_irq_int_6 : 1; /* RW */ | ||
| 593 | unsigned long lb_irq_int_7 : 1; /* RW */ | ||
| 594 | unsigned long lb_irq_int_8 : 1; /* RW */ | ||
| 595 | unsigned long lb_irq_int_9 : 1; /* RW */ | ||
| 596 | unsigned long lb_irq_int_10 : 1; /* RW */ | ||
| 597 | unsigned long lb_irq_int_11 : 1; /* RW */ | ||
| 598 | unsigned long lb_irq_int_12 : 1; /* RW */ | ||
| 599 | unsigned long lb_irq_int_13 : 1; /* RW */ | ||
| 600 | unsigned long lb_irq_int_14 : 1; /* RW */ | ||
| 601 | unsigned long lb_irq_int_15 : 1; /* RW */ | ||
| 602 | unsigned long l1_nmi_int : 1; /* RW */ | ||
| 603 | unsigned long stop_clock : 1; /* RW */ | ||
| 604 | unsigned long asic_to_l1 : 1; /* RW */ | ||
| 605 | unsigned long l1_to_asic : 1; /* RW */ | ||
| 606 | unsigned long ltc_int : 1; /* RW */ | ||
| 607 | unsigned long la_seq_trigger : 1; /* RW */ | ||
| 608 | unsigned long rsvd_45_63 : 19; /* */ | ||
| 609 | } s; | ||
| 610 | }; | ||
| 611 | |||
| 612 | /* ========================================================================= */ | ||
| 251 | /* UVH_NODE_ID */ | 613 | /* UVH_NODE_ID */ |
| 252 | /* ========================================================================= */ | 614 | /* ========================================================================= */ |
| 253 | #define UVH_NODE_ID 0x0UL | 615 | #define UVH_NODE_ID 0x0UL |
| @@ -284,6 +646,73 @@ union uvh_node_id_u { | |||
| 284 | }; | 646 | }; |
| 285 | 647 | ||
| 286 | /* ========================================================================= */ | 648 | /* ========================================================================= */ |
| 649 | /* UVH_NODE_PRESENT_TABLE */ | ||
| 650 | /* ========================================================================= */ | ||
| 651 | #define UVH_NODE_PRESENT_TABLE 0x1400UL | ||
| 652 | #define UVH_NODE_PRESENT_TABLE_DEPTH 16 | ||
| 653 | |||
| 654 | #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 | ||
| 655 | #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | ||
| 656 | |||
| 657 | union uvh_node_present_table_u { | ||
| 658 | unsigned long v; | ||
| 659 | struct uvh_node_present_table_s { | ||
| 660 | unsigned long nodes : 64; /* RW */ | ||
| 661 | } s; | ||
| 662 | }; | ||
| 663 | |||
| 664 | /* ========================================================================= */ | ||
| 665 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ | ||
| 666 | /* ========================================================================= */ | ||
| 667 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | ||
| 668 | |||
| 669 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | ||
| 670 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 671 | |||
| 672 | union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | ||
| 673 | unsigned long v; | ||
| 674 | struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { | ||
| 675 | unsigned long rsvd_0_23 : 24; /* */ | ||
| 676 | unsigned long dest_base : 22; /* RW */ | ||
| 677 | unsigned long rsvd_46_63: 18; /* */ | ||
| 678 | } s; | ||
| 679 | }; | ||
| 680 | |||
| 681 | /* ========================================================================= */ | ||
| 682 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ | ||
| 683 | /* ========================================================================= */ | ||
| 684 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | ||
| 685 | |||
| 686 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | ||
| 687 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 688 | |||
| 689 | union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | ||
| 690 | unsigned long v; | ||
| 691 | struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { | ||
| 692 | unsigned long rsvd_0_23 : 24; /* */ | ||
| 693 | unsigned long dest_base : 22; /* RW */ | ||
| 694 | unsigned long rsvd_46_63: 18; /* */ | ||
| 695 | } s; | ||
| 696 | }; | ||
| 697 | |||
| 698 | /* ========================================================================= */ | ||
| 699 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ | ||
| 700 | /* ========================================================================= */ | ||
| 701 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | ||
| 702 | |||
| 703 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | ||
| 704 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 705 | |||
| 706 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | ||
| 707 | unsigned long v; | ||
| 708 | struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { | ||
| 709 | unsigned long rsvd_0_23 : 24; /* */ | ||
| 710 | unsigned long dest_base : 22; /* RW */ | ||
| 711 | unsigned long rsvd_46_63: 18; /* */ | ||
| 712 | } s; | ||
| 713 | }; | ||
| 714 | |||
| 715 | /* ========================================================================= */ | ||
| 287 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ | 716 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ |
| 288 | /* ========================================================================= */ | 717 | /* ========================================================================= */ |
| 289 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | 718 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL |
| @@ -369,5 +798,77 @@ union uvh_si_addr_map_config_u { | |||
| 369 | } s; | 798 | } s; |
| 370 | }; | 799 | }; |
| 371 | 800 | ||
| 801 | /* ========================================================================= */ | ||
| 802 | /* UVH_SI_ALIAS0_OVERLAY_CONFIG */ | ||
| 803 | /* ========================================================================= */ | ||
| 804 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL | ||
| 805 | |||
| 806 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24 | ||
| 807 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | ||
| 808 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | ||
| 809 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | ||
| 810 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63 | ||
| 811 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | ||
| 812 | |||
| 813 | union uvh_si_alias0_overlay_config_u { | ||
| 814 | unsigned long v; | ||
| 815 | struct uvh_si_alias0_overlay_config_s { | ||
| 816 | unsigned long rsvd_0_23: 24; /* */ | ||
| 817 | unsigned long base : 8; /* RW */ | ||
| 818 | unsigned long rsvd_32_47: 16; /* */ | ||
| 819 | unsigned long m_alias : 5; /* RW */ | ||
| 820 | unsigned long rsvd_53_62: 10; /* */ | ||
| 821 | unsigned long enable : 1; /* RW */ | ||
| 822 | } s; | ||
| 823 | }; | ||
| 824 | |||
| 825 | /* ========================================================================= */ | ||
| 826 | /* UVH_SI_ALIAS1_OVERLAY_CONFIG */ | ||
| 827 | /* ========================================================================= */ | ||
| 828 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL | ||
| 829 | |||
| 830 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24 | ||
| 831 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | ||
| 832 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | ||
| 833 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | ||
| 834 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63 | ||
| 835 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | ||
| 836 | |||
| 837 | union uvh_si_alias1_overlay_config_u { | ||
| 838 | unsigned long v; | ||
| 839 | struct uvh_si_alias1_overlay_config_s { | ||
| 840 | unsigned long rsvd_0_23: 24; /* */ | ||
| 841 | unsigned long base : 8; /* RW */ | ||
| 842 | unsigned long rsvd_32_47: 16; /* */ | ||
| 843 | unsigned long m_alias : 5; /* RW */ | ||
| 844 | unsigned long rsvd_53_62: 10; /* */ | ||
| 845 | unsigned long enable : 1; /* RW */ | ||
| 846 | } s; | ||
| 847 | }; | ||
| 848 | |||
| 849 | /* ========================================================================= */ | ||
| 850 | /* UVH_SI_ALIAS2_OVERLAY_CONFIG */ | ||
| 851 | /* ========================================================================= */ | ||
| 852 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL | ||
| 853 | |||
| 854 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24 | ||
| 855 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | ||
| 856 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | ||
| 857 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | ||
| 858 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63 | ||
| 859 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | ||
| 860 | |||
| 861 | union uvh_si_alias2_overlay_config_u { | ||
| 862 | unsigned long v; | ||
| 863 | struct uvh_si_alias2_overlay_config_s { | ||
| 864 | unsigned long rsvd_0_23: 24; /* */ | ||
| 865 | unsigned long base : 8; /* RW */ | ||
| 866 | unsigned long rsvd_32_47: 16; /* */ | ||
| 867 | unsigned long m_alias : 5; /* RW */ | ||
| 868 | unsigned long rsvd_53_62: 10; /* */ | ||
| 869 | unsigned long enable : 1; /* RW */ | ||
| 870 | } s; | ||
| 871 | }; | ||
| 872 | |||
| 372 | 873 | ||
| 373 | #endif /* __ASM_X86_UV_MMRS__ */ | 874 | #endif /* __ASM_X86_UV_MMRS__ */ |