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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-sparc64/mmu.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-sparc64/mmu.h')
-rw-r--r--include/asm-sparc64/mmu.h99
1 files changed, 99 insertions, 0 deletions
diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h
new file mode 100644
index 000000000000..8627eed6e83d
--- /dev/null
+++ b/include/asm-sparc64/mmu.h
@@ -0,0 +1,99 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4#include <linux/config.h>
5#include <asm/page.h>
6#include <asm/const.h>
7
8/*
9 * For the 8k pagesize kernel, use only 10 hw context bits to optimize some
10 * shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically
11 * for vpte offset calculation). For other pagesizes, this optimization in
12 * the tlbhandlers can not be done; but still, all 13 bits can not be used
13 * because the tlb handlers use "andcc" instruction which sign extends 13
14 * bit arguments.
15 */
16#if PAGE_SHIFT == 13
17#define CTX_NR_BITS 10
18#else
19#define CTX_NR_BITS 12
20#endif
21
22#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
23
24/* UltraSPARC-III+ and later have a feature whereby you can
25 * select what page size the various Data-TLB instances in the
26 * chip. In order to gracefully support this, we put the version
27 * field in a spot outside of the areas of the context register
28 * where this parameter is specified.
29 */
30#define CTX_VERSION_SHIFT 22
31#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
32
33#define CTX_PGSZ_8KB _AC(0x0,UL)
34#define CTX_PGSZ_64KB _AC(0x1,UL)
35#define CTX_PGSZ_512KB _AC(0x2,UL)
36#define CTX_PGSZ_4MB _AC(0x3,UL)
37#define CTX_PGSZ_BITS _AC(0x7,UL)
38#define CTX_PGSZ0_NUC_SHIFT 61
39#define CTX_PGSZ1_NUC_SHIFT 58
40#define CTX_PGSZ0_SHIFT 16
41#define CTX_PGSZ1_SHIFT 19
42#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
43 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
44
45#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
46#define CTX_PGSZ_BASE CTX_PGSZ_8KB
47#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
48#define CTX_PGSZ_BASE CTX_PGSZ_64KB
49#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)
50#define CTX_PGSZ_BASE CTX_PGSZ_512KB
51#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)
52#define CTX_PGSZ_BASE CTX_PGSZ_4MB
53#else
54#error No page size specified in kernel configuration
55#endif
56
57#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
58#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
59#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
60#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
61#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
62#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
63#endif
64
65#define CTX_PGSZ_KERN CTX_PGSZ_4MB
66
67/* Thus, when running on UltraSPARC-III+ and later, we use the following
68 * PRIMARY_CONTEXT register values for the kernel context.
69 */
70#define CTX_CHEETAH_PLUS_NUC \
71 ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
72 (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
73
74#define CTX_CHEETAH_PLUS_CTX0 \
75 ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
76 (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
77
78/* If you want "the TLB context number" use CTX_NR_MASK. If you
79 * want "the bits I program into the context registers" use
80 * CTX_HW_MASK.
81 */
82#define CTX_NR_MASK TAG_CONTEXT_BITS
83#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
84
85#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
86#define CTX_VALID(__ctx) \
87 (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
88#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
89#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
90
91#ifndef __ASSEMBLY__
92
93typedef struct {
94 unsigned long sparc64_ctx_val;
95} mm_context_t;
96
97#endif /* !__ASSEMBLY__ */
98
99#endif /* __MMU_H */