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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-20 20:39:28 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-20 20:39:28 -0400
commitbe883da7594b0a2a02074e683673ae0e522566a4 (patch)
treeb62f2a8a069fb4d389935c0b2de9bc78798f50c2 /include/asm-sparc64/irq.h
parent077e98945db7e54a9865b5f29a1f02f531eca414 (diff)
parent4c5eb38af2131d867842cdd09fa83a3ed77bfd26 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Update defconfig. [SPARC64]: Don't double-export synchronize_irq. [SPARC64]: Move over to GENERIC_HARDIRQS. [SPARC64]: Virtualize IRQ numbers. [SPARC64]: Kill ino_bucket->pil [SPARC]: Kill __irq_itoa(). [SPARC64]: bp->pil can never be zero [SPARC64]: Send all device interrupts via one PIL. [SPARC]: Fix iommu_flush_iotlb end address [SPARC]: Mark smp init functions as cpuinit [SPARC]: Add missing rw can_lock macros [SPARC]: Setup cpu_possible_map [SPARC]: Add topology_init()
Diffstat (limited to 'include/asm-sparc64/irq.h')
-rw-r--r--include/asm-sparc64/irq.h96
1 files changed, 12 insertions, 84 deletions
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index fa164d37ee3f..905e59b4a737 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -15,58 +15,6 @@
15#include <asm/pil.h> 15#include <asm/pil.h>
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17 17
18struct ino_bucket;
19
20#define MAX_IRQ_DESC_ACTION 4
21
22struct irq_desc {
23 void (*pre_handler)(struct ino_bucket *, void *, void *);
24 void *pre_handler_arg1;
25 void *pre_handler_arg2;
26 u32 action_active_mask;
27 struct irqaction action[MAX_IRQ_DESC_ACTION];
28};
29
30/* You should not mess with this directly. That's the job of irq.c.
31 *
32 * If you make changes here, please update hand coded assembler of
33 * the vectored interrupt trap handler in entry.S -DaveM
34 *
35 * This is currently one DCACHE line, two buckets per L2 cache
36 * line. Keep this in mind please.
37 */
38struct ino_bucket {
39 /* Next handler in per-CPU PIL worklist. We know that
40 * bucket pointers have the high 32-bits clear, so to
41 * save space we only store the bits we need.
42 */
43/*0x00*/unsigned int irq_chain;
44
45 /* PIL to schedule this IVEC at. */
46/*0x04*/unsigned char pil;
47
48 /* If an IVEC arrives while irq_info is NULL, we
49 * set this to notify request_irq() about the event.
50 */
51/*0x05*/unsigned char pending;
52
53 /* Miscellaneous flags. */
54/*0x06*/unsigned char flags;
55
56 /* Currently unused. */
57/*0x07*/unsigned char __pad;
58
59 /* Reference to IRQ descriptor for this bucket. */
60/*0x08*/struct irq_desc *irq_info;
61
62 /* Sun5 Interrupt Clear Register. */
63/*0x10*/unsigned long iclr;
64
65 /* Sun5 Interrupt Mapping Register. */
66/*0x18*/unsigned long imap;
67
68};
69
70/* IMAP/ICLR register defines */ 18/* IMAP/ICLR register defines */
71#define IMAP_VALID 0x80000000 /* IRQ Enabled */ 19#define IMAP_VALID 0x80000000 /* IRQ Enabled */
72#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ 20#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
@@ -84,36 +32,20 @@ struct ino_bucket {
84#define ICLR_TRANSMIT 0x00000001 /* Transmit state */ 32#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
85#define ICLR_PENDING 0x00000003 /* Pending state */ 33#define ICLR_PENDING 0x00000003 /* Pending state */
86 34
87/* Only 8-bits are available, be careful. -DaveM */ 35/* The largest number of unique interrupt sources we support.
88#define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */ 36 * If this needs to ever be larger than 255, you need to change
89#define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/ 37 * the type of ino_bucket->virt_irq as appropriate.
90#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */ 38 *
91 39 * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
92#define NUM_IVECS (IMAP_INR + 1) 40 */
93extern struct ino_bucket ivector_table[NUM_IVECS]; 41#define NR_IRQS 255
94
95#define __irq_ino(irq) \
96 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
97#define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
98#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
99#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
100
101static __inline__ char *__irq_itoa(unsigned int irq)
102{
103 static char buff[16];
104
105 sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
106 return buff;
107}
108
109#define NR_IRQS 16
110 42
43extern void irq_install_pre_handler(int virt_irq,
44 void (*func)(unsigned int, void *, void *),
45 void *arg1, void *arg2);
111#define irq_canonicalize(irq) (irq) 46#define irq_canonicalize(irq) (irq)
112extern void disable_irq(unsigned int); 47extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
113#define disable_irq_nosync disable_irq 48extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
114extern void enable_irq(unsigned int);
115extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
116extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags);
117extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); 49extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
118 50
119static __inline__ void set_softint(unsigned long bits) 51static __inline__ void set_softint(unsigned long bits)
@@ -139,8 +71,4 @@ static __inline__ unsigned long get_softint(void)
139 return retval; 71 return retval;
140} 72}
141 73
142struct irqaction;
143struct pt_regs;
144int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
145
146#endif 74#endif