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authorDavid S. Miller <davem@davemloft.net>2008-02-23 23:38:20 -0500
committerDavid S. Miller <davem@davemloft.net>2008-02-23 23:38:20 -0500
commit8d3c202be23c5a915f7053ebd4e96f44700c6a62 (patch)
treee0f017aff86d3ad0b858fe85f44e11096087ed00 /include/asm-sh/io.h
parent1b04ab4597725f75f94942da9aa40daa7b9a4bd9 (diff)
parent038eb0ea04b245351be34b0ae76b55eee4603989 (diff)
Merge branch 'master' of ../linux-2.6/
Diffstat (limited to 'include/asm-sh/io.h')
-rw-r--r--include/asm-sh/io.h22
1 files changed, 16 insertions, 6 deletions
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 94900c089519..356e50d06745 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -38,6 +38,7 @@
38 */ 38 */
39#define __IO_PREFIX generic 39#define __IO_PREFIX generic
40#include <asm/io_generic.h> 40#include <asm/io_generic.h>
41#include <asm/io_trapped.h>
41 42
42#define maybebadio(port) \ 43#define maybebadio(port) \
43 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \ 44 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
@@ -181,13 +182,13 @@ __BUILD_MEMORY_STRING(w, u16)
181#define iowrite32(v,a) writel((v),(a)) 182#define iowrite32(v,a) writel((v),(a))
182#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a)) 183#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
183 184
184#define ioread8_rep(a,d,c) insb((a),(d),(c)) 185#define ioread8_rep(a, d, c) readsb((a), (d), (c))
185#define ioread16_rep(a,d,c) insw((a),(d),(c)) 186#define ioread16_rep(a, d, c) readsw((a), (d), (c))
186#define ioread32_rep(a,d,c) insl((a),(d),(c)) 187#define ioread32_rep(a, d, c) readsl((a), (d), (c))
187 188
188#define iowrite8_rep(a,s,c) outsb((a),(s),(c)) 189#define iowrite8_rep(a, s, c) writesb((a), (s), (c))
189#define iowrite16_rep(a,s,c) outsw((a),(s),(c)) 190#define iowrite16_rep(a, s, c) writesw((a), (s), (c))
190#define iowrite32_rep(a,s,c) outsl((a),(s),(c)) 191#define iowrite32_rep(a, s, c) writesl((a), (s), (c))
191 192
192#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */ 193#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
193 194
@@ -207,6 +208,8 @@ static inline void __set_io_port_base(unsigned long pbase)
207 generic_io_base = pbase; 208 generic_io_base = pbase;
208} 209}
209 210
211#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
212
210/* We really want to try and get these to memcpy etc */ 213/* We really want to try and get these to memcpy etc */
211extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long); 214extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
212extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long); 215extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
@@ -309,7 +312,14 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
309{ 312{
310#ifdef CONFIG_SUPERH32 313#ifdef CONFIG_SUPERH32
311 unsigned long last_addr = offset + size - 1; 314 unsigned long last_addr = offset + size - 1;
315#endif
316 void __iomem *ret;
312 317
318 ret = __ioremap_trapped(offset, size);
319 if (ret)
320 return ret;
321
322#ifdef CONFIG_SUPERH32
313 /* 323 /*
314 * For P1 and P2 space this is trivial, as everything is already 324 * For P1 and P2 space this is trivial, as everything is already
315 * mapped. Uncached access for P1 addresses are done through P2. 325 * mapped. Uncached access for P1 addresses are done through P2.