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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-27 11:49:07 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-27 11:49:07 -0400
commitb98adfccdf5f8dd34ae56a2d5adbe2c030bd4674 (patch)
tree1807a029520f550dd4f90c95ad0063bceb00d645 /include/asm-sh/cpu-sh3/ubc.h
parentba21fe71725f94792330ebc3034ef2b35a36276f (diff)
parent33573c0e3243aaa38b6ad96942de85a1b713c2ff (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (108 commits) sh: Fix occasional flush_cache_4096() stack corruption. sh: Calculate shm alignment at runtime. sh: dma-mapping compile fixes. sh: Initial vsyscall page support. sh: Clean up PAGE_SIZE definition for assembly use. sh: Selective flush_cache_mm() flushing. sh: More intelligent entry_mask/way_size calculation. sh: Support for L2 cache on newer SH-4A CPUs. sh: Update kexec support for API changes. sh: Optimized readsl()/writesl() support. sh: Report movli.l/movco.l capabilities. sh: CPU flags in AT_HWCAP in ELF auxvt. sh: Add support for 4K stacks. sh: Enable /proc/kcore support. sh: stack debugging support. sh: select CONFIG_EMBEDDED. sh: machvec rework. sh: Solution Engine SH7343 board support. sh: SH7710VoIPGW board support. sh: Enable verbose BUG() support. ...
Diffstat (limited to 'include/asm-sh/cpu-sh3/ubc.h')
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h15
1 files changed, 14 insertions, 1 deletions
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 0f809dec4e17..9d308cbe9b29 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -11,6 +11,19 @@
11#ifndef __ASM_CPU_SH3_UBC_H 11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710)
15#define UBC_BARA 0xa4ffffb0
16#define UBC_BAMRA 0xa4ffffb4
17#define UBC_BBRA 0xa4ffffb8
18#define UBC_BASRA 0xffffffe4
19#define UBC_BARB 0xa4ffffa0
20#define UBC_BAMRB 0xa4ffffa4
21#define UBC_BBRB 0xa4ffffa8
22#define UBC_BASRB 0xffffffe8
23#define UBC_BDRB 0xa4ffff90
24#define UBC_BDMRB 0xa4ffff94
25#define UBC_BRCR 0xa4ffff98
26#else
14#define UBC_BARA 0xffffffb0 27#define UBC_BARA 0xffffffb0
15#define UBC_BAMRA 0xffffffb4 28#define UBC_BAMRA 0xffffffb4
16#define UBC_BBRA 0xffffffb8 29#define UBC_BBRA 0xffffffb8
@@ -22,6 +35,6 @@
22#define UBC_BDRB 0xffffff90 35#define UBC_BDRB 0xffffff90
23#define UBC_BDMRB 0xffffff94 36#define UBC_BDMRB 0xffffff94
24#define UBC_BRCR 0xffffff98 37#define UBC_BRCR 0xffffff98
38#endif
25 39
26#endif /* __ASM_CPU_SH3_UBC_H */ 40#endif /* __ASM_CPU_SH3_UBC_H */
27