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authorMatt Porter <mporter@kernel.crashing.org>2005-08-01 01:34:52 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-08-01 22:14:01 -0400
commitc9cf73aee140baa425429902aaed2c758401343f (patch)
tree7e28361e87950e7e66a453e4218745a4b0912119 /include/asm-ppc/ibm44x.h
parente8be1c8e065691c332fd8e9bae70c7096a69c31d (diff)
[PATCH] ppc32: add 440ep support
Add PPC440EP core support. PPC440EP is a PPC440-based SoC with a classic PPC FPU and another set of peripherals. Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com> Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc/ibm44x.h')
-rw-r--r--include/asm-ppc/ibm44x.h34
1 files changed, 31 insertions, 3 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 87f051138b9d..21e41c9b7267 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -35,8 +35,10 @@
35#define PPC44x_LOW_SLOT 63 35#define PPC44x_LOW_SLOT 63
36 36
37/* LS 32-bits of UART0 physical address location for early serial text debug */ 37/* LS 32-bits of UART0 physical address location for early serial text debug */
38#ifdef CONFIG_440SP 38#if defined(CONFIG_440SP)
39#define UART0_PHYS_IO_BASE 0xf0000200 39#define UART0_PHYS_IO_BASE 0xf0000200
40#elif defined(CONFIG_440EP)
41#define UART0_PHYS_IO_BASE 0xe0000000
40#else 42#else
41#define UART0_PHYS_IO_BASE 0x40000200 43#define UART0_PHYS_IO_BASE 0x40000200
42#endif 44#endif
@@ -49,11 +51,16 @@
49/* 51/*
50 * Standard 4GB "page" definitions 52 * Standard 4GB "page" definitions
51 */ 53 */
52#ifdef CONFIG_440SP 54#if defined(CONFIG_440SP)
53#define PPC44x_IO_PAGE 0x0000000100000000ULL 55#define PPC44x_IO_PAGE 0x0000000100000000ULL
54#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 56#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
55#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 57#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
56#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 58#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
59#elif defined(CONFIG_440EP)
60#define PPC44x_IO_PAGE 0x0000000000000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
57#else 64#else
58#define PPC44x_IO_PAGE 0x0000000100000000ULL 65#define PPC44x_IO_PAGE 0x0000000100000000ULL
59#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL 66#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
64/* 71/*
65 * 36-bit trap ranges 72 * 36-bit trap ranges
66 */ 73 */
67#ifdef CONFIG_440SP 74#if defined(CONFIG_440SP)
68#define PPC44x_IO_LO 0xf0000000UL 75#define PPC44x_IO_LO 0xf0000000UL
69#define PPC44x_IO_HI 0xf0000fffUL 76#define PPC44x_IO_HI 0xf0000fffUL
70#define PPC44x_PCI0CFG_LO 0x0ec00000UL 77#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
75#define PPC44x_PCI2CFG_HI 0x2ec00007UL 82#define PPC44x_PCI2CFG_HI 0x2ec00007UL
76#define PPC44x_PCIMEM_LO 0x80000000UL 83#define PPC44x_PCIMEM_LO 0x80000000UL
77#define PPC44x_PCIMEM_HI 0xdfffffffUL 84#define PPC44x_PCIMEM_HI 0xdfffffffUL
85#elif defined(CONFIG_440EP)
86#define PPC44x_IO_LO 0xef500000UL
87#define PPC44x_IO_HI 0xefffffffUL
88#define PPC44x_PCI0CFG_LO 0xeec00000UL
89#define PPC44x_PCI0CFG_HI 0xeecfffffUL
90#define PPC44x_PCIMEM_LO 0xa0000000UL
91#define PPC44x_PCIMEM_HI 0xdfffffffUL
78#else 92#else
79#define PPC44x_IO_LO 0x40000000UL 93#define PPC44x_IO_LO 0x40000000UL
80#define PPC44x_IO_HI 0x40000fffUL 94#define PPC44x_IO_HI 0x40000fffUL
@@ -152,6 +166,12 @@
152#define DCRN_SDR_UART0 0x0120 166#define DCRN_SDR_UART0 0x0120
153#define DCRN_SDR_UART1 0x0121 167#define DCRN_SDR_UART1 0x0121
154 168
169#ifdef CONFIG_440EP
170#define DCRN_SDR_UART2 0x0122
171#define DCRN_SDR_UART3 0x0123
172#define DCRN_SDR_CUST0 0x4000
173#endif
174
155/* SDR read/write helper macros */ 175/* SDR read/write helper macros */
156#define SDR_READ(offset) ({\ 176#define SDR_READ(offset) ({\
157 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 177 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
169#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 189#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
170#define DCRN_MAL_BASE 0x180 190#define DCRN_MAL_BASE 0x180
171 191
192#ifdef CONFIG_440EP
193#define DCRN_DMA2P40_BASE 0x300
194#define DCRN_DMA2P41_BASE 0x308
195#define DCRN_DMA2P42_BASE 0x310
196#define DCRN_DMA2P43_BASE 0x318
197#define DCRN_DMA2P4SR_BASE 0x320
198#endif
199
172/* UIC */ 200/* UIC */
173#define DCRN_UIC0_BASE 0xc0 201#define DCRN_UIC0_BASE 0xc0
174#define DCRN_UIC1_BASE 0xd0 202#define DCRN_UIC1_BASE 0xd0