diff options
author | Paul Mackerras <paulus@samba.org> | 2008-06-09 00:01:46 -0400 |
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committer | Paul Mackerras <paulus@samba.org> | 2008-06-10 07:40:22 -0400 |
commit | 917f0af9e5a9ceecf9e72537fabb501254ba321d (patch) | |
tree | 1ef207755c6d83ce4af93ef2b5e4645eebd65886 /include/asm-ppc/gg2.h | |
parent | 0f3d6bcd391b058c619fc30e8022e8a29fbf4bef (diff) |
powerpc: Remove arch/ppc and include/asm-ppc
All the maintained platforms are now in arch/powerpc, so the old
arch/ppc stuff can now go away.
Acked-by: Adrian Bunk <bunk@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Jochen Friedrich <jochen@scram.de>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Sean MacLennan <smaclennan@pikatech.com>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-ppc/gg2.h')
-rw-r--r-- | include/asm-ppc/gg2.h | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h deleted file mode 100644 index 341ae55b99fb..000000000000 --- a/include/asm-ppc/gg2.h +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions | ||
3 | * | ||
4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
5 | * | ||
6 | * This file is based on the following documentation: | ||
7 | * | ||
8 | * The VAS96011/12 Chipset, Data Book, Edition 1.0 | ||
9 | * VLSI Technology, Inc. | ||
10 | * | ||
11 | * This file is subject to the terms and conditions of the GNU General Public | ||
12 | * License. See the file COPYING in the main directory of this archive | ||
13 | * for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _ASMPPC_GG2_H | ||
17 | #define _ASMPPC_GG2_H | ||
18 | |||
19 | /* | ||
20 | * Memory Map (CHRP mode) | ||
21 | */ | ||
22 | |||
23 | #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ | ||
24 | #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ | ||
25 | #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ | ||
26 | #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ | ||
27 | #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ | ||
28 | /* special PCI cycles */ | ||
29 | #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ | ||
30 | #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ | ||
31 | |||
32 | |||
33 | /* | ||
34 | * GG2 specific PCI Registers | ||
35 | */ | ||
36 | |||
37 | extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ | ||
38 | |||
39 | #define GG2_PCI_BUSNO 0x40 /* Bus number */ | ||
40 | #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ | ||
41 | #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ | ||
42 | #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ | ||
43 | #define GG2_PCI_ADDR_MAP 0x5c /* Address map */ | ||
44 | #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ | ||
45 | #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ | ||
46 | #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ | ||
47 | #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ | ||
48 | #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ | ||
49 | #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ | ||
50 | #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ | ||
51 | #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ | ||
52 | #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ | ||
53 | #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ | ||
54 | #define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ | ||
55 | #define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ | ||
56 | #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ | ||
57 | #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ | ||
58 | #define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ | ||
59 | /* Cleared when read */ | ||
60 | |||
61 | #endif /* _ASMPPC_GG2_H */ | ||