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authorRalf Baechle <ralf@linux-mips.org>2007-07-06 09:40:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-06 11:17:11 -0400
commitfde97822a295da9dffa4af643b49a58ffc4516ad (patch)
treef9e10d270a8616ad092d9cdeddf20bb8e7c29b14 /include/asm-mips
parent075c733e19ce7530b53b78151cc4d303c8f64548 (diff)
[MIPS] Add macros to encode processor revisions.
Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/cpu.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d38fdbf845b2..2924069075e0 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -125,6 +125,17 @@
125#define PRID_REV_VR4130 0x0080 125#define PRID_REV_VR4130 0x0080
126 126
127/* 127/*
128 * Older processors used to encode processor version and revision in two
129 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
130 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
131 * the patch number. *ARGH*
132 */
133#define PRID_REV_ENCODE_44(ver, rev) \
134 ((ver) << 4 | (rev))
135#define PRID_REV_ENCODE_332(ver, rev, patch) \
136 ((ver) << 5 | (rev) << 2 | (patch))
137
138/*
128 * FPU implementation/revision register (CP1 control register 0). 139 * FPU implementation/revision register (CP1 control register 0).
129 * 140 *
130 * +---------------------------------+----------------+----------------+ 141 * +---------------------------------+----------------+----------------+