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authorKevin D. Kissell <kevink@mips.com>2007-08-03 13:38:03 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:45:57 -0400
commitf571eff0a24ed97a919f2b61bb4afdeab4b43002 (patch)
treee9d6c597fafca02720f000cf795a37f2d163f10f /include/asm-mips
parentbbf25010f1a6b761914430f5fca081ec8c7accd1 (diff)
[MIPS] IRQ Affinity Support for SMTC on Malta Platform
Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/irq.h67
-rw-r--r--include/asm-mips/smtc_ipi.h1
2 files changed, 66 insertions, 2 deletions
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 2cb52cf8bd4e..a58f0eecc68f 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -46,6 +46,38 @@ static inline void smtc_im_ack_irq(unsigned int irq)
46 46
47#endif /* CONFIG_MIPS_MT_SMTC */ 47#endif /* CONFIG_MIPS_MT_SMTC */
48 48
49#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
50#include <linux/cpumask.h>
51
52extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity);
53extern void smtc_forward_irq(unsigned int irq);
54
55/*
56 * IRQ affinity hook invoked at the beginning of interrupt dispatch
57 * if option is enabled.
58 *
59 * Up through Linux 2.6.22 (at least) cpumask operations are very
60 * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
61 * used a "fast path" per-IRQ-descriptor cache of affinity information
62 * to reduce latency. As there is a project afoot to optimize the
63 * cpumask implementations, this version is optimistically assuming
64 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
65 */
66#define IRQ_AFFINITY_HOOK(irq) \
67do { \
68 if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \
69 smtc_forward_irq(irq); \
70 irq_exit(); \
71 return; \
72 } \
73} while (0)
74
75#else /* Not doing SMTC affinity */
76
77#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
78
79#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
80
49#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP 81#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
50 82
51/* 83/*
@@ -56,13 +88,27 @@ static inline void smtc_im_ack_irq(unsigned int irq)
56 */ 88 */
57#define __DO_IRQ_SMTC_HOOK(irq) \ 89#define __DO_IRQ_SMTC_HOOK(irq) \
58do { \ 90do { \
91 IRQ_AFFINITY_HOOK(irq); \
59 if (irq_hwmask[irq] & 0x0000ff00) \ 92 if (irq_hwmask[irq] & 0x0000ff00) \
60 write_c0_tccontext(read_c0_tccontext() & \ 93 write_c0_tccontext(read_c0_tccontext() & \
61 ~(irq_hwmask[irq] & 0x0000ff00)); \ 94 ~(irq_hwmask[irq] & 0x0000ff00)); \
95} while (0)
96
97#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
98do { \
99 if (irq_hwmask[irq] & 0x0000ff00) \
100 write_c0_tccontext(read_c0_tccontext() & \
101 ~(irq_hwmask[irq] & 0x0000ff00)); \
62} while (0) 102} while (0)
103
63#else 104#else
64 105
65#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) 106#define __DO_IRQ_SMTC_HOOK(irq) \
107do { \
108 IRQ_AFFINITY_HOOK(irq); \
109} while (0)
110#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
111
66#endif 112#endif
67 113
68/* 114/*
@@ -81,6 +127,23 @@ do { \
81 irq_exit(); \ 127 irq_exit(); \
82} while (0) 128} while (0)
83 129
130#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
131/*
132 * To avoid inefficient and in some cases pathological re-checking of
133 * IRQ affinity, we have this variant that skips the affinity check.
134 */
135
136
137#define do_IRQ_no_affinity(irq) \
138do { \
139 irq_enter(); \
140 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
141 generic_handle_irq(irq); \
142 irq_exit(); \
143} while (0)
144
145#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
146
84extern void arch_init_irq(void); 147extern void arch_init_irq(void);
85extern void spurious_interrupt(void); 148extern void spurious_interrupt(void);
86 149
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h
index a52a4a7a36e0..e09131a6127d 100644
--- a/include/asm-mips/smtc_ipi.h
+++ b/include/asm-mips/smtc_ipi.h
@@ -34,6 +34,7 @@ struct smtc_ipi {
34 34
35#define LINUX_SMP_IPI 1 35#define LINUX_SMP_IPI 1
36#define SMTC_CLOCK_TICK 2 36#define SMTC_CLOCK_TICK 2
37#define IRQ_AFFINITY_IPI 3
37 38
38/* 39/*
39 * A queue of IPI messages 40 * A queue of IPI messages