Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Increase cp0 compare clockevent min_delta_ns from 0x30 to 0x300.
  [MIPS] Cache: Provide more information on cache policy on bootup.
  [MIPS] Fix aliasing bug in copy_user_highpage, take 2.
  [MIPS] VPE loader: convert from struct class_ device to struct device
  [MIPS] MIPSsim: Fix booting from NFS root
  [MIPS] Alchemy: Get rid of au1xxx_irq_map_t.
  [MIPS] Alchemy: Get rid of au_ffz().
  [MIPS] Alchemy: Get rid of au_ffs().
  [MIPS] Alchemy: cleanup interrupt code.
  [MIPS] Lasat: Fix build by conversion to irq_cpu.c.
  [MIPS] Lasat: Add #ifndef ... #endif include warpper to lasatint.h.
  [MIPS] IP22: Enable -Werror.
  [MIPS] IP22: Fix warning.
  [MIPS] IP22: Complain if requesting the front panel irq failed.
  [MIPS] vmlinux.lds.S: Handle KPROBES_TEXT.
  [MIPS] vmlinux.lds.S: Fix handling of .notes in final link.
  [MIPS] vmlinux.lds.S: Remove duplicate comment.
  [MIPS] MSP71XX: Add workarounds file.
  [MIPS] IP32: Fix build by conversion to irq_cpu.c.

5 files changed, 129 insertions, 93 deletions

diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index c3c280e3d591..042f821899a8 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -9,86 +9,104 @@
 #ifndef __ASM_IP32_INTS_H
 #define __ASM_IP32_INTS_H
 
+#include <asm/irq.h>
+
 /*
  * This list reflects the assignment of interrupt numbers to
  * interrupting events.  Order is fairly irrelevant to handling
  * priority.  This differs from irix.
  */
 
-/* CPU */
-#define IP32_R4K_TIMER_IRQ              0
+enum ip32_irq_no {
+        /*
+         * CPU interrupts are 0 ... 7
+         */
 
-/* MACE */
-#define MACE_VID_IN1_IRQ                1
-#define MACE_VID_IN2_IRQ                2
-#define MACE_VID_OUT_IRQ                3
-#define MACE_ETHERNET_IRQ               4
-/* SUPERIO, MISC, and AUDIO are MACEISA */
-#define MACE_PCI_BRIDGE_IRQ             8
+        /*
+         * MACE
+         */
+        MACE_VID_IN1_IRQ                = MIPS_CPU_IRQ_BASE + 8,
+        MACE_VID_IN2_IRQ,
+        MACE_VID_OUT_IRQ,
+        MACE_ETHERNET_IRQ,
+        /* SUPERIO, MISC, and AUDIO are MACEISA */
+        __MACE_SUPERIO,
+        __MACE_MISC,
+        __MACE_AUDIO,
+        MACE_PCI_BRIDGE_IRQ,
 
-/* MACEPCI */
-#define MACEPCI_SCSI0_IRQ               9
-#define MACEPCI_SCSI1_IRQ               10
-#define MACEPCI_SLOT0_IRQ               11
-#define MACEPCI_SLOT1_IRQ               12
-#define MACEPCI_SLOT2_IRQ               13
-#define MACEPCI_SHARED0_IRQ             14
-#define MACEPCI_SHARED1_IRQ             15
-#define MACEPCI_SHARED2_IRQ             16
+        /*
+         * MACEPCI
+         */
+        MACEPCI_SCSI0_IRQ,
+        MACEPCI_SCSI1_IRQ,
+        MACEPCI_SLOT0_IRQ,
+        MACEPCI_SLOT1_IRQ,
+        MACEPCI_SLOT2_IRQ,
+        MACEPCI_SHARED0_IRQ,
+        MACEPCI_SHARED1_IRQ,
+        MACEPCI_SHARED2_IRQ,
 
-/* CRIME */
-#define CRIME_GBE0_IRQ                  17
-#define CRIME_GBE1_IRQ                  18
-#define CRIME_GBE2_IRQ                  19
-#define CRIME_GBE3_IRQ                  20
-#define CRIME_CPUERR_IRQ                21
-#define CRIME_MEMERR_IRQ                22
-#define CRIME_RE_EMPTY_E_IRQ            23
-#define CRIME_RE_FULL_E_IRQ             24
-#define CRIME_RE_IDLE_E_IRQ             25
-#define CRIME_RE_EMPTY_L_IRQ            26
-#define CRIME_RE_FULL_L_IRQ             27
-#define CRIME_RE_IDLE_L_IRQ             28
-#define CRIME_SOFT0_IRQ                 29
-#define CRIME_SOFT1_IRQ                 30
-#define CRIME_SOFT2_IRQ                 31
-#define CRIME_SYSCORERR_IRQ             CRIME_SOFT2_IRQ
-#define CRIME_VICE_IRQ                  32
+        /*
+         * CRIME
+         */
+        CRIME_GBE0_IRQ,
+        CRIME_GBE1_IRQ,
+        CRIME_GBE2_IRQ,
+        CRIME_GBE3_IRQ,
+        CRIME_CPUERR_IRQ,
+        CRIME_MEMERR_IRQ,
+        CRIME_RE_EMPTY_E_IRQ,
+        CRIME_RE_FULL_E_IRQ,
+        CRIME_RE_IDLE_E_IRQ,
+        CRIME_RE_EMPTY_L_IRQ,
+        CRIME_RE_FULL_L_IRQ,
+        CRIME_RE_IDLE_L_IRQ,
+        CRIME_SOFT0_IRQ,
+        CRIME_SOFT1_IRQ,
+        CRIME_SOFT2_IRQ,
+        CRIME_SYSCORERR_IRQ             = CRIME_SOFT2_IRQ,
+        CRIME_VICE_IRQ,
 
-/* MACEISA */
-#define MACEISA_AUDIO_SW_IRQ            33
-#define MACEISA_AUDIO_SC_IRQ            34
-#define MACEISA_AUDIO1_DMAT_IRQ         35
-#define MACEISA_AUDIO1_OF_IRQ           36
-#define MACEISA_AUDIO2_DMAT_IRQ         37
-#define MACEISA_AUDIO2_MERR_IRQ         38
-#define MACEISA_AUDIO3_DMAT_IRQ         39
-#define MACEISA_AUDIO3_MERR_IRQ         40
-#define MACEISA_RTC_IRQ                 41
-#define MACEISA_KEYB_IRQ                42
-/* MACEISA_KEYB_POLL is not an IRQ */
-#define MACEISA_MOUSE_IRQ               44
-/* MACEISA_MOUSE_POLL is not an IRQ */
-#define MACEISA_TIMER0_IRQ              46
-#define MACEISA_TIMER1_IRQ              47
-#define MACEISA_TIMER2_IRQ              48
-#define MACEISA_PARALLEL_IRQ            49
-#define MACEISA_PAR_CTXA_IRQ            50
-#define MACEISA_PAR_CTXB_IRQ            51
-#define MACEISA_PAR_MERR_IRQ            52
-#define MACEISA_SERIAL1_IRQ             53
-#define MACEISA_SERIAL1_TDMAT_IRQ       54
-#define MACEISA_SERIAL1_TDMAPR_IRQ      55
-#define MACEISA_SERIAL1_TDMAME_IRQ      56
-#define MACEISA_SERIAL1_RDMAT_IRQ       57
-#define MACEISA_SERIAL1_RDMAOR_IRQ      58
-#define MACEISA_SERIAL2_IRQ             59
-#define MACEISA_SERIAL2_TDMAT_IRQ       60
-#define MACEISA_SERIAL2_TDMAPR_IRQ      61
-#define MACEISA_SERIAL2_TDMAME_IRQ      62
-#define MACEISA_SERIAL2_RDMAT_IRQ       63
-#define MACEISA_SERIAL2_RDMAOR_IRQ      64
+        /*
+         * MACEISA
+         */
+        MACEISA_AUDIO_SW_IRQ,
+        MACEISA_AUDIO_SC_IRQ,
+        MACEISA_AUDIO1_DMAT_IRQ,
+        MACEISA_AUDIO1_OF_IRQ,
+        MACEISA_AUDIO2_DMAT_IRQ,
+        MACEISA_AUDIO2_MERR_IRQ,
+        MACEISA_AUDIO3_DMAT_IRQ,
+        MACEISA_AUDIO3_MERR_IRQ,
+        MACEISA_RTC_IRQ,
+        MACEISA_KEYB_IRQ,
+        /* MACEISA_KEYB_POLL is not an IRQ */
+        __MACEISA_KEYB_POLL,
+        MACEISA_MOUSE_IRQ,
+        /* MACEISA_MOUSE_POLL is not an IRQ */
+        __MACEISA_MOUSE_POLL,
+        MACEISA_TIMER0_IRQ,
+        MACEISA_TIMER1_IRQ,
+        MACEISA_TIMER2_IRQ,
+        MACEISA_PARALLEL_IRQ,
+        MACEISA_PAR_CTXA_IRQ,
+        MACEISA_PAR_CTXB_IRQ,
+        MACEISA_PAR_MERR_IRQ,
+        MACEISA_SERIAL1_IRQ,
+        MACEISA_SERIAL1_TDMAT_IRQ,
+        MACEISA_SERIAL1_TDMAPR_IRQ,
+        MACEISA_SERIAL1_TDMAME_IRQ,
+        MACEISA_SERIAL1_RDMAT_IRQ,
+        MACEISA_SERIAL1_RDMAOR_IRQ,
+        MACEISA_SERIAL2_IRQ,
+        MACEISA_SERIAL2_TDMAT_IRQ,
+        MACEISA_SERIAL2_TDMAPR_IRQ,
+        MACEISA_SERIAL2_TDMAME_IRQ,
+        MACEISA_SERIAL2_RDMAT_IRQ,
+        MACEISA_SERIAL2_RDMAOR_IRQ,
 
-#define IP32_IRQ_MAX                    MACEISA_SERIAL2_RDMAOR_IRQ
+        IP32_IRQ_MAX                    = MACEISA_SERIAL2_RDMAOR_IRQ
+};
 
 #endif /* __ASM_IP32_INTS_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
index 065474feeccc..581dc45685a2 100644
--- a/include/asm-mips/lasat/lasatint.h
+++ b/include/asm-mips/lasat/lasatint.h
@@ -1,4 +1,10 @@
-#define LASATINT_END 16
+#ifndef __ASM_LASAT_LASATINT_H
+#define __ASM_LASAT_LASATINT_H
+
+#include <linux/irq.h>
+
+#define LASATINT_BASE   MIPS_CPU_IRQ_BASE
+#define LASATINT_END    (LASATINT_BASE + 16)
 
 /* lasat 100 */
 #define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
@@ -10,3 +16,4 @@
 #define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
 #define LASATINT_MASK_SHIFT_200         16
 
+#endif /* __ASM_LASAT_LASATINT_H */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 10f613f23c33..b37baf8cf624 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -91,23 +91,6 @@ static inline u32 au_readl(unsigned long reg)
 }
 
 
-static __inline__ int au_ffz(unsigned int x)
-{
-        if ((x = ~x) == 0)
-                return 32;
-        return __ilog2(x & -x);
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int au_ffs(int x)
-{
-        return __ilog2(x & -x) + 1;
-}
-
 /* arch/mips/au1000/common/clocks.c */
 extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
@@ -119,16 +102,16 @@ extern unsigned int get_au1x00_lcd_clock(void);
 /*
  * Every board describes its IRQ mapping with this table.
  */
-typedef struct au1xxx_irqmap {
+struct au1xxx_irqmap {
         int     im_irq;
         int     im_type;
         int     im_request;
-} au1xxx_irq_map_t;
+};
 
 /*
  * init_IRQ looks for a table with this name.
  */
-extern au1xxx_irq_map_t au1xxx_irq_map[];
+extern struct au1xxx_irqmap au1xxx_irq_map[];
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/include/asm-mips/pmc-sierra/msp71xx/war.h
new file mode 100644
index 000000000000..0bf48fc1892b
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
+#define __ASM_MIPS_PMC_SIERRA_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+        defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+
+#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 85b44366343a..786f7e3c99bc 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -86,9 +86,9 @@ struct pt_regs {
 
 extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
 
-extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
+extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET;
 
-static inline void die_if_kernel(const char *str, struct pt_regs *regs)
+static inline void die_if_kernel(const char *str, const struct pt_regs *regs)
 {
         if (unlikely(!user_mode(regs)))
                 die(str, regs);