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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-10-01 06:35:28 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-10-01 18:16:59 -0400
commit998ec2901aea9f412d2dc3e29a3c20f377793916 (patch)
treecb6a15e7445b5ac018342b17f9d39cda03f0a8fd /include/asm-mips
parentb00f3774f2e073d399ffbd0475337466938e9273 (diff)
[MIPS] Add UART IRQ number for EV64120
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/mach-ev64120/mach-gt64120.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
index 13b1443a7a65..7e272ce57ea3 100644
--- a/include/asm-mips/mach-ev64120/mach-gt64120.h
+++ b/include/asm-mips/mach-ev64120/mach-gt64120.h
@@ -42,6 +42,7 @@ extern unsigned long gt64120_base;
42#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) 42#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
43#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) 43#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
44#define EV64120_BASE_BAUD ( 3686400 / 16 ) 44#define EV64120_BASE_BAUD ( 3686400 / 16 )
45#define EV64120_UART_IRQ 6
45 46
46/* 47/*
47 * PCI interrupts will come in on either the INTA or INTD interrups lines, 48 * PCI interrupts will come in on either the INTA or INTD interrups lines,