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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2008-01-04 17:31:07 -0500
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 05:14:59 -0500
commit231a35d37293ab88d325a9cb94e5474c156282c0 (patch)
tree75f38d069e5e49de03fb789975b8a102c282b979 /include/asm-mips
parent237cfee1db66147aef4457f02b56a41e6f84bfd3 (diff)
[MIPS] RM: Collected changes
- EISA support for non PCI RMs (RM200 and RM400-xxx). The major part is the splitting of the EISA and onboard ISA of the RM200, which makes the EISA bus on the RM200 look like on other RMs. - 64bit kernel support - system type detection is now common for big and little endian - moved sniprom code to arch/mips/fw - added call_o32 function to arch/mips/fw/lib, which uses a private stack for calling prom functions - fix problem with ISA interrupts, which makes using PIT clockevent possible Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/bootinfo.h1
-rw-r--r--include/asm-mips/mipsprom.h2
-rw-r--r--include/asm-mips/sni.h159
3 files changed, 94 insertions, 68 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 8e9bb16f0aa2..e031bdff9920 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -96,6 +96,7 @@
96 96
97#define CL_SIZE COMMAND_LINE_SIZE 97#define CL_SIZE COMMAND_LINE_SIZE
98 98
99extern char *system_type;
99const char *get_system_type(void); 100const char *get_system_type(void);
100 101
101extern unsigned long mips_machtype; 102extern unsigned long mips_machtype;
diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h
index ce7cff7f1e8e..146d41b67adc 100644
--- a/include/asm-mips/mipsprom.h
+++ b/include/asm-mips/mipsprom.h
@@ -71,4 +71,6 @@
71#define PROM_NV_GET 53 /* XXX */ 71#define PROM_NV_GET 53 /* XXX */
72#define PROM_NV_SET 54 /* XXX */ 72#define PROM_NV_SET 54 /* XXX */
73 73
74extern char *prom_getenv(char *);
75
74#endif /* __ASM_MIPS_PROM_H */ 76#endif /* __ASM_MIPS_PROM_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index af081457f847..e716447e5e03 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -35,23 +35,23 @@ extern unsigned int sni_brd_type;
35#define SNI_CPU_M8050 0x0b 35#define SNI_CPU_M8050 0x0b
36#define SNI_CPU_M8053 0x0d 36#define SNI_CPU_M8053 0x0d
37 37
38#define SNI_PORT_BASE 0xb4000000 38#define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
39 39
40#ifndef __MIPSEL__ 40#ifndef __MIPSEL__
41/* 41/*
42 * ASIC PCI registers for big endian configuration. 42 * ASIC PCI registers for big endian configuration.
43 */ 43 */
44#define PCIMT_UCONF 0xbfff0004 44#define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
45#define PCIMT_IOADTIMEOUT2 0xbfff000c 45#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
46#define PCIMT_IOMEMCONF 0xbfff0014 46#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
47#define PCIMT_IOMMU 0xbfff001c 47#define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
48#define PCIMT_IOADTIMEOUT1 0xbfff0024 48#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
49#define PCIMT_DMAACCESS 0xbfff002c 49#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
50#define PCIMT_DMAHIT 0xbfff0034 50#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
51#define PCIMT_ERRSTATUS 0xbfff003c 51#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
52#define PCIMT_ERRADDR 0xbfff0044 52#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
53#define PCIMT_SYNDROME 0xbfff004c 53#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
54#define PCIMT_ITPEND 0xbfff0054 54#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
55#define IT_INT2 0x01 55#define IT_INT2 0x01
56#define IT_INTD 0x02 56#define IT_INTD 0x02
57#define IT_INTC 0x04 57#define IT_INTC 0x04
@@ -60,32 +60,32 @@ extern unsigned int sni_brd_type;
60#define IT_EISA 0x20 60#define IT_EISA 0x20
61#define IT_SCSI 0x40 61#define IT_SCSI 0x40
62#define IT_ETH 0x80 62#define IT_ETH 0x80
63#define PCIMT_IRQSEL 0xbfff005c 63#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
64#define PCIMT_TESTMEM 0xbfff0064 64#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
65#define PCIMT_ECCREG 0xbfff006c 65#define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
66#define PCIMT_CONFIG_ADDRESS 0xbfff0074 66#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
67#define PCIMT_ASIC_ID 0xbfff007c /* read */ 67#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
68#define PCIMT_SOFT_RESET 0xbfff007c /* write */ 68#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
69#define PCIMT_PIA_OE 0xbfff0084 69#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
70#define PCIMT_PIA_DATAOUT 0xbfff008c 70#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
71#define PCIMT_PIA_DATAIN 0xbfff0094 71#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
72#define PCIMT_CACHECONF 0xbfff009c 72#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
73#define PCIMT_INVSPACE 0xbfff00a4 73#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
74#else 74#else
75/* 75/*
76 * ASIC PCI registers for little endian configuration. 76 * ASIC PCI registers for little endian configuration.
77 */ 77 */
78#define PCIMT_UCONF 0xbfff0000 78#define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
79#define PCIMT_IOADTIMEOUT2 0xbfff0008 79#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
80#define PCIMT_IOMEMCONF 0xbfff0010 80#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
81#define PCIMT_IOMMU 0xbfff0018 81#define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
82#define PCIMT_IOADTIMEOUT1 0xbfff0020 82#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
83#define PCIMT_DMAACCESS 0xbfff0028 83#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
84#define PCIMT_DMAHIT 0xbfff0030 84#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
85#define PCIMT_ERRSTATUS 0xbfff0038 85#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
86#define PCIMT_ERRADDR 0xbfff0040 86#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
87#define PCIMT_SYNDROME 0xbfff0048 87#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
88#define PCIMT_ITPEND 0xbfff0050 88#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
89#define IT_INT2 0x01 89#define IT_INT2 0x01
90#define IT_INTD 0x02 90#define IT_INTD 0x02
91#define IT_INTC 0x04 91#define IT_INTC 0x04
@@ -94,20 +94,20 @@ extern unsigned int sni_brd_type;
94#define IT_EISA 0x20 94#define IT_EISA 0x20
95#define IT_SCSI 0x40 95#define IT_SCSI 0x40
96#define IT_ETH 0x80 96#define IT_ETH 0x80
97#define PCIMT_IRQSEL 0xbfff0058 97#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
98#define PCIMT_TESTMEM 0xbfff0060 98#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
99#define PCIMT_ECCREG 0xbfff0068 99#define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
100#define PCIMT_CONFIG_ADDRESS 0xbfff0070 100#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
101#define PCIMT_ASIC_ID 0xbfff0078 /* read */ 101#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
102#define PCIMT_SOFT_RESET 0xbfff0078 /* write */ 102#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
103#define PCIMT_PIA_OE 0xbfff0080 103#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
104#define PCIMT_PIA_DATAOUT 0xbfff0088 104#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
105#define PCIMT_PIA_DATAIN 0xbfff0090 105#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
106#define PCIMT_CACHECONF 0xbfff0098 106#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
107#define PCIMT_INVSPACE 0xbfff00a0 107#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
108#endif 108#endif
109 109
110#define PCIMT_PCI_CONF 0xbfff0100 110#define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
111 111
112/* 112/*
113 * Data port for the PCI bus in IO space 113 * Data port for the PCI bus in IO space
@@ -117,34 +117,34 @@ extern unsigned int sni_brd_type;
117/* 117/*
118 * Board specific registers 118 * Board specific registers
119 */ 119 */
120#define PCIMT_CSMSR 0xbfd00000 120#define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
121#define PCIMT_CSSWITCH 0xbfd10000 121#define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
122#define PCIMT_CSITPEND 0xbfd20000 122#define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
123#define PCIMT_AUTO_PO_EN 0xbfd30000 123#define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
124#define PCIMT_CLR_TEMP 0xbfd40000 124#define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
125#define PCIMT_AUTO_PO_DIS 0xbfd50000 125#define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
126#define PCIMT_EXMSR 0xbfd60000 126#define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
127#define PCIMT_UNUSED1 0xbfd70000 127#define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
128#define PCIMT_CSWCSM 0xbfd80000 128#define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
129#define PCIMT_UNUSED2 0xbfd90000 129#define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
130#define PCIMT_CSLED 0xbfda0000 130#define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
131#define PCIMT_CSMAPISA 0xbfdb0000 131#define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
132#define PCIMT_CSRSTBP 0xbfdc0000 132#define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
133#define PCIMT_CLRPOFF 0xbfdd0000 133#define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
134#define PCIMT_CSTIMER 0xbfde0000 134#define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
135#define PCIMT_PWDN 0xbfdf0000 135#define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
136 136
137/* 137/*
138 * A20R based boards 138 * A20R based boards
139 */ 139 */
140#define A20R_PT_CLOCK_BASE 0xbc040000 140#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
141#define A20R_PT_TIM0_ACK 0xbc050000 141#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
142#define A20R_PT_TIM1_ACK 0xbc060000 142#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
143 143
144#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE 144#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
145#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) 145#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
146 146
147#define SNI_PCIT_INT_REG 0xbfff000c 147#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
148 148
149#define SNI_PCIT_INT_START 24 149#define SNI_PCIT_INT_START 24
150#define SNI_PCIT_INT_END 30 150#define SNI_PCIT_INT_END 30
@@ -186,10 +186,30 @@ extern unsigned int sni_brd_type;
186/* 186/*
187 * Base address for the mapped 16mb EISA bus segment. 187 * Base address for the mapped 16mb EISA bus segment.
188 */ 188 */
189#define PCIMT_EISA_BASE 0xb0000000 189#define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
190 190
191/* PCI EISA Interrupt acknowledge */ 191/* PCI EISA Interrupt acknowledge */
192#define PCIMT_INT_ACKNOWLEDGE 0xba000000 192#define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
193
194/*
195 * SNI ID PROM
196 *
197 * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities
198 * SNI_IDPROM_BRDTYPE Board Type
199 * SNI_IDPROM_CPUTYPE CPU Type on RM400
200 */
201#ifdef CONFIG_CPU_BIG_ENDIAN
202#define __SNI_END 0
203#endif
204#ifdef CONFIG_CPU_LITTLE_ENDIAN
205#define __SNI_END 3
206#endif
207#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)
208#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
209#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
210#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
211
212#define SNI_IDPROM_SIZE 0x1000
193 213
194/* board specific init functions */ 214/* board specific init functions */
195extern void sni_a20r_init(void); 215extern void sni_a20r_init(void);
@@ -207,6 +227,9 @@ extern void sni_pcimt_irq_init(void);
207/* timer inits */ 227/* timer inits */
208extern void sni_cpu_time_init(void); 228extern void sni_cpu_time_init(void);
209 229
230/* eisa init for RM200/400 */
231extern int sni_eisa_root_init(void);
232
210/* common irq stuff */ 233/* common irq stuff */
211extern void (*sni_hwint)(void); 234extern void (*sni_hwint)(void);
212extern struct irqaction sni_isa_irq; 235extern struct irqaction sni_isa_irq;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 10:30:29 -0400