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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-10 11:33:08 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:35 -0400
commit89d63fe179520b11f54de1f26755b7444c79e73a (patch)
treefede06c5648335652c864fc35c951d991cbab183 /include/asm-mips/txx9
parent22b1d707ffc99faebd86257ad19d5bb9fc624734 (diff)
[MIPS] TXx9: Reorganize PCI code
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/txx9')
-rw-r--r--include/asm-mips/txx9/generic.h23
-rw-r--r--include/asm-mips/txx9/pci.h36
-rw-r--r--include/asm-mips/txx9/rbtx4927.h29
-rw-r--r--include/asm-mips/txx9/tx3927.h4
-rw-r--r--include/asm-mips/txx9/tx4927.h318
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h199
-rw-r--r--include/asm-mips/txx9/tx4938.h226
7 files changed, 454 insertions, 381 deletions
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
new file mode 100644
index 000000000000..2ff6c2002204
--- /dev/null
+++ b/include/asm-mips/txx9/generic.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm-mips/txx9/generic.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8#ifndef __ASM_TXX9_GENERIC_H
9#define __ASM_TXX9_GENERIC_H
10
11#include <linux/init.h>
12#include <linux/ioport.h> /* for struct resource */
13
14extern struct resource txx9_ce_res[];
15extern char txx9_pcode_str[8];
16void txx9_reg_res_init(unsigned int pcode, unsigned long base,
17 unsigned long size);
18
19extern unsigned int txx9_master_clock;
20extern unsigned int txx9_cpu_clock;
21extern unsigned int txx9_gbus_clock;
22
23#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
new file mode 100644
index 000000000000..d89a45091e24
--- /dev/null
+++ b/include/asm-mips/txx9/pci.h
@@ -0,0 +1,36 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef __ASM_TXX9_PCI_H
7#define __ASM_TXX9_PCI_H
8
9#include <linux/pci.h>
10
11extern struct pci_controller txx9_primary_pcic;
12struct pci_controller *
13txx9_alloc_pci_controller(struct pci_controller *pcic,
14 unsigned long mem_base, unsigned long mem_size,
15 unsigned long io_base, unsigned long io_size);
16
17int txx9_pci66_check(struct pci_controller *hose, int top_bus,
18 int current_bus);
19extern int txx9_pci_mem_high __initdata;
20
21extern int txx9_pci_option;
22#define TXX9_PCI_OPT_PICMG 0x0002
23#define TXX9_PCI_OPT_CLK_33 0x0008
24#define TXX9_PCI_OPT_CLK_66 0x0010
25#define TXX9_PCI_OPT_CLK_MASK \
26 (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
27#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
28
29enum txx9_pci_err_action {
30 TXX9_PCI_ERR_REPORT,
31 TXX9_PCI_ERR_IGNORE,
32 TXX9_PCI_ERR_PANIC,
33};
34extern enum txx9_pci_err_action txx9_pci_err_action;
35
36#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index 5531342bcc01..5b6f488b1b3c 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -29,10 +29,33 @@
29 29
30#include <asm/txx9/tx4927.h> 30#include <asm/txx9/tx4927.h>
31 31
32#define RBTX4927_PCIMEM 0x08000000
33#define RBTX4927_PCIMEM_SIZE 0x08000000
34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000
36
37#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL)
38
39/* bits for ISTAT/IMASK/IMSTAT */
40#define RBTX4927_INTB_PCID 0
41#define RBTX4927_INTB_PCIC 1
42#define RBTX4927_INTB_PCIB 2
43#define RBTX4927_INTB_PCIA 3
44#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
45#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
46#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
47#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
48
49#define RBTX4927_IRQ_IOC (TX4927_IRQ_PIC_BEG + TX4927_NUM_IR)
50#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
51#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
52#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
53#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
54
32#ifdef CONFIG_PCI 55#ifdef CONFIG_PCI
33#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO 56#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
34#else 57#else
35#define TBTX4927_ISA_IO_OFFSET 0 58#define RBTX4927_ISA_IO_OFFSET 0
36#endif 59#endif
37 60
38#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL 61#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
@@ -41,7 +64,7 @@
41#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL 64#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
42#define RBTX4927_SW_RESET_ENABLE_SET 0x01 65#define RBTX4927_SW_RESET_ENABLE_SET 0x01
43 66
44#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 67#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
45#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) 68#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
46 69
47int toshiba_rbtx4927_irq_nested(int sw_irq); 70int toshiba_rbtx4927_irq_nested(int sw_irq);
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
index 63b62d6061f5..ca414c7624e1 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -316,4 +316,8 @@ struct tx3927_ccfg_reg {
316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) 317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
318 318
319struct pci_controller;
320void __init tx3927_pcic_setup(struct pci_controller *channel,
321 unsigned long sdram_size, int extarb);
322
319#endif /* __ASM_TXX9_TX3927_H */ 323#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index f21a7b1831e5..c0382fd2ae7f 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -27,7 +27,10 @@
27#ifndef __ASM_TXX9_TX4927_H 27#ifndef __ASM_TXX9_TX4927_H
28#define __ASM_TXX9_TX4927_H 28#define __ASM_TXX9_TX4927_H
29 29
30#include <linux/types.h>
31#include <linux/io.h>
30#include <asm/txx9irq.h> 32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h>
31 34
32#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE 35#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
33#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) 36#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
@@ -43,15 +46,6 @@
43 46
44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) 47#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
45 48
46#define TX4927_CCFG_TOE 0x00004000
47#define TX4927_CCFG_WR 0x00008000
48#define TX4927_CCFG_TINTDIS 0x01000000
49
50#define TX4927_PCIMEM 0x08000000
51#define TX4927_PCIMEM_SIZE 0x08000000
52#define TX4927_PCIIO 0x16000000
53#define TX4927_PCIIO_SIZE 0x01000000
54
55#define TX4927_SDRAMC_REG 0xff1f8000 49#define TX4927_SDRAMC_REG 0xff1f8000
56#define TX4927_EBUSC_REG 0xff1f9000 50#define TX4927_EBUSC_REG 0xff1f9000
57#define TX4927_PCIC_REG 0xff1fd000 51#define TX4927_PCIC_REG 0xff1fd000
@@ -60,36 +54,9 @@
60#define TX4927_NR_TMR 3 54#define TX4927_NR_TMR 3
61#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) 55#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
62 56
63/* bits for ISTAT3/IMASK3/IMSTAT3 */
64#define TX4927_INT3B_PCID 0
65#define TX4927_INT3B_PCIC 1
66#define TX4927_INT3B_PCIB 2
67#define TX4927_INT3B_PCIA 3
68#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
69#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
70#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
71#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
72
73#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
74#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
75
76#define TX4927_IR_PCIC 16 57#define TX4927_IR_PCIC 16
77#define TX4927_IR_PCIERR 22 58#define TX4927_IR_PCIERR 22
78#define TX4927_IR_PCIPMA 23 59#define TX4927_NUM_IR 32
79#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
80#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
81#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
82#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
83#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
84#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
85#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
86
87#ifdef _LANGUAGE_ASSEMBLY
88#define _CONST64(c) c
89#else
90#define _CONST64(c) c##ull
91
92#include <asm/byteorder.h>
93 60
94struct tx4927_sdramc_reg { 61struct tx4927_sdramc_reg {
95 volatile unsigned long long cr[4]; 62 volatile unsigned long long cr[4];
@@ -104,177 +71,158 @@ struct tx4927_ebusc_reg {
104}; 71};
105 72
106struct tx4927_ccfg_reg { 73struct tx4927_ccfg_reg {
107 volatile unsigned long long ccfg; 74 u64 ccfg;
108 volatile unsigned long long crir; 75 u64 crir;
109 volatile unsigned long long pcfg; 76 u64 pcfg;
110 volatile unsigned long long tear; 77 u64 toea;
111 volatile unsigned long long clkctr; 78 u64 clkctr;
112 volatile unsigned long long unused0; 79 u64 unused0;
113 volatile unsigned long long garbc; 80 u64 garbc;
114 volatile unsigned long long unused1; 81 u64 unused1;
115 volatile unsigned long long unused2; 82 u64 unused2;
116 volatile unsigned long long ramp; 83 u64 ramp;
117};
118
119struct tx4927_pcic_reg {
120 volatile unsigned long pciid;
121 volatile unsigned long pcistatus;
122 volatile unsigned long pciccrev;
123 volatile unsigned long pcicfg1;
124 volatile unsigned long p2gm0plbase; /* +10 */
125 volatile unsigned long p2gm0pubase;
126 volatile unsigned long p2gm1plbase;
127 volatile unsigned long p2gm1pubase;
128 volatile unsigned long p2gm2pbase; /* +20 */
129 volatile unsigned long p2giopbase;
130 volatile unsigned long unused0;
131 volatile unsigned long pcisid;
132 volatile unsigned long unused1; /* +30 */
133 volatile unsigned long pcicapptr;
134 volatile unsigned long unused2;
135 volatile unsigned long pcicfg2;
136 volatile unsigned long g2ptocnt; /* +40 */
137 volatile unsigned long unused3[15];
138 volatile unsigned long g2pstatus; /* +80 */
139 volatile unsigned long g2pmask;
140 volatile unsigned long pcisstatus;
141 volatile unsigned long pcimask;
142 volatile unsigned long p2gcfg; /* +90 */
143 volatile unsigned long p2gstatus;
144 volatile unsigned long p2gmask;
145 volatile unsigned long p2gccmd;
146 volatile unsigned long unused4[24]; /* +a0 */
147 volatile unsigned long pbareqport; /* +100 */
148 volatile unsigned long pbacfg;
149 volatile unsigned long pbastatus;
150 volatile unsigned long pbamask;
151 volatile unsigned long pbabm; /* +110 */
152 volatile unsigned long pbacreq;
153 volatile unsigned long pbacgnt;
154 volatile unsigned long pbacstate;
155 volatile unsigned long long g2pmgbase[3]; /* +120 */
156 volatile unsigned long long g2piogbase;
157 volatile unsigned long g2pmmask[3]; /* +140 */
158 volatile unsigned long g2piomask;
159 volatile unsigned long long g2pmpbase[3]; /* +150 */
160 volatile unsigned long long g2piopbase;
161 volatile unsigned long pciccfg; /* +170 */
162 volatile unsigned long pcicstatus;
163 volatile unsigned long pcicmask;
164 volatile unsigned long unused5;
165 volatile unsigned long long p2gmgbase[3]; /* +180 */
166 volatile unsigned long long p2giogbase;
167 volatile unsigned long g2pcfgadrs; /* +1a0 */
168 volatile unsigned long g2pcfgdata;
169 volatile unsigned long unused6[8];
170 volatile unsigned long g2pintack;
171 volatile unsigned long g2pspc;
172 volatile unsigned long unused7[12]; /* +1d0 */
173 volatile unsigned long long pdmca; /* +200 */
174 volatile unsigned long long pdmga;
175 volatile unsigned long long pdmpa;
176 volatile unsigned long long pdmcut;
177 volatile unsigned long long pdmcnt; /* +220 */
178 volatile unsigned long long pdmsts;
179 volatile unsigned long long unused8[2];
180 volatile unsigned long long pdmdb[4]; /* +240 */
181 volatile unsigned long long pdmtdh; /* +260 */
182 volatile unsigned long long pdmdms;
183}; 84};
184 85
185#endif /* _LANGUAGE_ASSEMBLY */
186
187/*
188 * PCIC
189 */
190
191/* bits for G2PSTATUS/G2PMASK */
192#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
193#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
194#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
195
196/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
197#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
198
199/* bits for PBACFG */
200#define TX4927_PCIC_PBACFG_RPBA 0x00000004
201#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
202#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
203
204/* bits for G2PMnGBASE */
205#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
206#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
207
208/* bits for G2PIOGBASE */
209#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
210#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
211
212/* bits for PCICSTATUS/PCICMASK */
213#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
214
215/* bits for PCICCFG */
216#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
217#define TX4927_PCIC_PCICCFG_HRST 0x00000800
218#define TX4927_PCIC_PCICCFG_SRST 0x00000400
219#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
220#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
221#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
222#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
223#define TX4927_PCIC_PCICCFG_IISE 0x00000020
224#define TX4927_PCIC_PCICCFG_ATR 0x00000010
225#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
226
227/* bits for P2GMnGBASE */
228#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
229#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
230#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
231
232/* bits for P2GIOGBASE */
233#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
234#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
235#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
236
237#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
238#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
239
240/* 86/*
241 * CCFG 87 * CCFG
242 */ 88 */
243/* CCFG : Chip Configuration */ 89/* CCFG : Chip Configuration */
90#define TX4927_CCFG_WDRST 0x0000020000000000ULL
91#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
92#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
93#define TX4927_CCFG_TINTDIS 0x01000000
244#define TX4927_CCFG_PCI66 0x00800000 94#define TX4927_CCFG_PCI66 0x00800000
245#define TX4927_CCFG_PCIMIDE 0x00400000 95#define TX4927_CCFG_PCIMODE 0x00400000
246#define TX4927_CCFG_PCIXARB 0x00002000 96#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
97#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
98#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
99#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
100#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
101#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
102#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
103#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
104#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
105#define TX4927_CCFG_BEOW 0x00010000
106#define TX4927_CCFG_WR 0x00008000
107#define TX4927_CCFG_TOE 0x00004000
108#define TX4927_CCFG_PCIARB 0x00002000
247#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 109#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
248#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 110#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
249#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 111#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
250#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 112#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
251#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 113#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
252 114#define TX4927_CCFG_SYSSP_MASK 0x000000c0
253#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 115#define TX4927_CCFG_ENDIAN 0x00000004
254#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 116#define TX4927_CCFG_HALT 0x00000002
255#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 117#define TX4927_CCFG_ACEHOLD 0x00000001
256#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 118#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
257#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
258#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
259#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
260#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
261#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
262 119
263/* PCFG : Pin Configuration */ 120/* PCFG : Pin Configuration */
121#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
122#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
123#define TX4927_PCFG_SYSCLKEN 0x08000000
124#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
125#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
264#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 126#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
265#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) 127#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
128#define TX4927_PCFG_SEL2 0x00000200
129#define TX4927_PCFG_SEL1 0x00000100
130#define TX4927_PCFG_DMASEL_ALL 0x000000ff
131#define TX4927_PCFG_DMASEL0_MASK 0x00000003
132#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
133#define TX4927_PCFG_DMASEL2_MASK 0x00000030
134#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
135#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
136#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
137#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
138#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
139#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
140#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
141#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
142#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
143#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
144#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
145#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
146#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
147#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
148#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
149#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
150#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
151#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
266 152
267/* CLKCTR : Clock Control */ 153/* CLKCTR : Clock Control */
154#define TX4927_CLKCTR_ACLCKD 0x02000000
155#define TX4927_CLKCTR_PIOCKD 0x01000000
156#define TX4927_CLKCTR_DMACKD 0x00800000
268#define TX4927_CLKCTR_PCICKD 0x00400000 157#define TX4927_CLKCTR_PCICKD 0x00400000
158#define TX4927_CLKCTR_TM0CKD 0x00100000
159#define TX4927_CLKCTR_TM1CKD 0x00080000
160#define TX4927_CLKCTR_TM2CKD 0x00040000
161#define TX4927_CLKCTR_SIO0CKD 0x00020000
162#define TX4927_CLKCTR_SIO1CKD 0x00010000
163#define TX4927_CLKCTR_ACLRST 0x00000200
164#define TX4927_CLKCTR_PIORST 0x00000100
165#define TX4927_CLKCTR_DMARST 0x00000080
269#define TX4927_CLKCTR_PCIRST 0x00000040 166#define TX4927_CLKCTR_PCIRST 0x00000040
270 167#define TX4927_CLKCTR_TM0RST 0x00000010
271#ifndef _LANGUAGE_ASSEMBLY 168#define TX4927_CLKCTR_TM1RST 0x00000008
169#define TX4927_CLKCTR_TM2RST 0x00000004
170#define TX4927_CLKCTR_SIO0RST 0x00000002
171#define TX4927_CLKCTR_SIO1RST 0x00000001
272 172
273#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) 173#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
274#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) 174#define tx4927_pcicptr \
275#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) 175 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
176#define tx4927_ccfgptr \
177 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
276#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 178#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
277 179
278#endif /* _LANGUAGE_ASSEMBLY */ 180/* utilities */
181static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
182{
183#ifdef CONFIG_32BIT
184 unsigned long flags;
185 local_irq_save(flags);
186#endif
187 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
188#ifdef CONFIG_32BIT
189 local_irq_restore(flags);
190#endif
191}
192static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
193{
194#ifdef CONFIG_32BIT
195 unsigned long flags;
196 local_irq_save(flags);
197#endif
198 ____raw_writeq(____raw_readq(adr) | bits, adr);
199#ifdef CONFIG_32BIT
200 local_irq_restore(flags);
201#endif
202}
203
204/* These functions are not interrupt safe. */
205static inline void tx4927_ccfg_clear(__u64 bits)
206{
207 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
208 & ~(TX4927_CCFG_W1CBITS | bits),
209 &tx4927_ccfgptr->ccfg);
210}
211static inline void tx4927_ccfg_set(__u64 bits)
212{
213 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
214 & ~TX4927_CCFG_W1CBITS) | bits,
215 &tx4927_ccfgptr->ccfg);
216}
217static inline void tx4927_ccfg_change(__u64 change, __u64 new)
218{
219 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
220 & ~(TX4927_CCFG_W1CBITS | change)) |
221 new,
222 &tx4927_ccfgptr->ccfg);
223}
224
225int tx4927_report_pciclk(void);
226int tx4927_pciclk66_setup(void);
279 227
280#endif /* __ASM_TXX9_TX4927_H */ 228#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..d61c3d09c4a2
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -0,0 +1,199 @@
1/*
2 * include/asm-mips/txx9/tx4927pcic.h
3 * TX4927 PCI controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9_TX4927PCIC_H
10#define __ASM_TXX9_TX4927PCIC_H
11
12#include <linux/pci.h>
13
14struct tx4927_pcic_reg {
15 u32 pciid;
16 u32 pcistatus;
17 u32 pciccrev;
18 u32 pcicfg1;
19 u32 p2gm0plbase; /* +10 */
20 u32 p2gm0pubase;
21 u32 p2gm1plbase;
22 u32 p2gm1pubase;
23 u32 p2gm2pbase; /* +20 */
24 u32 p2giopbase;
25 u32 unused0;
26 u32 pcisid;
27 u32 unused1; /* +30 */
28 u32 pcicapptr;
29 u32 unused2;
30 u32 pcicfg2;
31 u32 g2ptocnt; /* +40 */
32 u32 unused3[15];
33 u32 g2pstatus; /* +80 */
34 u32 g2pmask;
35 u32 pcisstatus;
36 u32 pcimask;
37 u32 p2gcfg; /* +90 */
38 u32 p2gstatus;
39 u32 p2gmask;
40 u32 p2gccmd;
41 u32 unused4[24]; /* +a0 */
42 u32 pbareqport; /* +100 */
43 u32 pbacfg;
44 u32 pbastatus;
45 u32 pbamask;
46 u32 pbabm; /* +110 */
47 u32 pbacreq;
48 u32 pbacgnt;
49 u32 pbacstate;
50 u64 g2pmgbase[3]; /* +120 */
51 u64 g2piogbase;
52 u32 g2pmmask[3]; /* +140 */
53 u32 g2piomask;
54 u64 g2pmpbase[3]; /* +150 */
55 u64 g2piopbase;
56 u32 pciccfg; /* +170 */
57 u32 pcicstatus;
58 u32 pcicmask;
59 u32 unused5;
60 u64 p2gmgbase[3]; /* +180 */
61 u64 p2giogbase;
62 u32 g2pcfgadrs; /* +1a0 */
63 u32 g2pcfgdata;
64 u32 unused6[8];
65 u32 g2pintack;
66 u32 g2pspc;
67 u32 unused7[12]; /* +1d0 */
68 u64 pdmca; /* +200 */
69 u64 pdmga;
70 u64 pdmpa;
71 u64 pdmctr;
72 u64 pdmcfg; /* +220 */
73 u64 pdmsts;
74};
75
76/* bits for PCICMD */
77/* see PCI_COMMAND_XXX in linux/pci_regs.h */
78
79/* bits for PCISTAT */
80/* see PCI_STATUS_XXX in linux/pci_regs.h */
81
82/* bits for IOBA/MBA */
83/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
84
85/* bits for G2PSTATUS/G2PMASK */
86#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
87#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
88#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
89
90/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
91#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
92
93/* bits for PBACFG */
94#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
95#define TX4927_PCIC_PBACFG_RPBA 0x00000004
96#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
97#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
98
99/* bits for PBASTATUS/PBAMASK */
100#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
101#define TX4927_PCIC_PBASTATUS_BM 0x00000001
102
103/* bits for G2PMnGBASE */
104#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
105#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
106
107/* bits for G2PIOGBASE */
108#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
109#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
110
111/* bits for PCICSTATUS/PCICMASK */
112#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
113#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
114#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
115#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
116#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
117#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
118#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
119#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
120#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
121#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
122
123/* bits for PCICCFG */
124#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
125#define TX4927_PCIC_PCICCFG_HRST 0x00000800
126#define TX4927_PCIC_PCICCFG_SRST 0x00000400
127#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
128#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
129#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
130#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
131#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
132#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
133#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
134#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
135
136/* bits for P2GMnGBASE */
137#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
138#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
139#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
140
141/* bits for P2GIOGBASE */
142#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
143#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
144#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
145
146#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
147#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
148
149/* bits for PDMCFG */
150#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
151#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
152#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
153#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
154#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
155#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
156#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
157#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
158#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
159#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
160#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
161#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
162#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
163#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
164#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
165#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
166#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
167#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
168#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
169#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
170#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
171#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
172#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
173
174/* bits for PDMSTS */
175#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
176#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
177#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
178#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
179#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
180#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
181#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
182#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
183#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
184#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
185#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
186#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
187#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
188#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
189#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
190#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
191#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
192
193struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
194 struct pci_controller *channel);
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb);
197void tx4927_report_pcic_status(void);
198
199#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 7f9cfef1c6d2..0bb891993b08 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -12,6 +12,9 @@
12#ifndef __ASM_TXX9_TX4938_H 12#ifndef __ASM_TXX9_TX4938_H
13#define __ASM_TXX9_TX4938_H 13#define __ASM_TXX9_TX4938_H
14 14
15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h>
17
15#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
16#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
17 20
@@ -51,9 +54,6 @@
51#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 54#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
52#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 55#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
53 56
54#ifdef __ASSEMBLY__
55#define _CONST64(c) c
56#else
57#define _CONST64(c) c##ull 57#define _CONST64(c) c##ull
58 58
59#include <asm/byteorder.h> 59#include <asm/byteorder.h>
@@ -113,68 +113,6 @@ struct tx4938_dma_reg {
113 endian_def_l2(unused0, mcr); 113 endian_def_l2(unused0, mcr);
114}; 114};
115 115
116struct tx4938_pcic_reg {
117 volatile unsigned long pciid;
118 volatile unsigned long pcistatus;
119 volatile unsigned long pciccrev;
120 volatile unsigned long pcicfg1;
121 volatile unsigned long p2gm0plbase; /* +10 */
122 volatile unsigned long p2gm0pubase;
123 volatile unsigned long p2gm1plbase;
124 volatile unsigned long p2gm1pubase;
125 volatile unsigned long p2gm2pbase; /* +20 */
126 volatile unsigned long p2giopbase;
127 volatile unsigned long unused0;
128 volatile unsigned long pcisid;
129 volatile unsigned long unused1; /* +30 */
130 volatile unsigned long pcicapptr;
131 volatile unsigned long unused2;
132 volatile unsigned long pcicfg2;
133 volatile unsigned long g2ptocnt; /* +40 */
134 volatile unsigned long unused3[15];
135 volatile unsigned long g2pstatus; /* +80 */
136 volatile unsigned long g2pmask;
137 volatile unsigned long pcisstatus;
138 volatile unsigned long pcimask;
139 volatile unsigned long p2gcfg; /* +90 */
140 volatile unsigned long p2gstatus;
141 volatile unsigned long p2gmask;
142 volatile unsigned long p2gccmd;
143 volatile unsigned long unused4[24]; /* +a0 */
144 volatile unsigned long pbareqport; /* +100 */
145 volatile unsigned long pbacfg;
146 volatile unsigned long pbastatus;
147 volatile unsigned long pbamask;
148 volatile unsigned long pbabm; /* +110 */
149 volatile unsigned long pbacreq;
150 volatile unsigned long pbacgnt;
151 volatile unsigned long pbacstate;
152 volatile unsigned long long g2pmgbase[3]; /* +120 */
153 volatile unsigned long long g2piogbase;
154 volatile unsigned long g2pmmask[3]; /* +140 */
155 volatile unsigned long g2piomask;
156 volatile unsigned long long g2pmpbase[3]; /* +150 */
157 volatile unsigned long long g2piopbase;
158 volatile unsigned long pciccfg; /* +170 */
159 volatile unsigned long pcicstatus;
160 volatile unsigned long pcicmask;
161 volatile unsigned long unused5;
162 volatile unsigned long long p2gmgbase[3]; /* +180 */
163 volatile unsigned long long p2giogbase;
164 volatile unsigned long g2pcfgadrs; /* +1a0 */
165 volatile unsigned long g2pcfgdata;
166 volatile unsigned long unused6[8];
167 volatile unsigned long g2pintack;
168 volatile unsigned long g2pspc;
169 volatile unsigned long unused7[12]; /* +1d0 */
170 volatile unsigned long long pdmca; /* +200 */
171 volatile unsigned long long pdmga;
172 volatile unsigned long long pdmpa;
173 volatile unsigned long long pdmctr;
174 volatile unsigned long long pdmcfg; /* +220 */
175 volatile unsigned long long pdmsts;
176};
177
178struct tx4938_aclc_reg { 116struct tx4938_aclc_reg {
179 volatile unsigned long acctlen; 117 volatile unsigned long acctlen;
180 volatile unsigned long acctldis; 118 volatile unsigned long acctldis;
@@ -262,18 +200,18 @@ struct tx4938_sramc_reg {
262}; 200};
263 201
264struct tx4938_ccfg_reg { 202struct tx4938_ccfg_reg {
265 volatile unsigned long long ccfg; 203 u64 ccfg;
266 volatile unsigned long long crir; 204 u64 crir;
267 volatile unsigned long long pcfg; 205 u64 pcfg;
268 volatile unsigned long long tear; 206 u64 toea;
269 volatile unsigned long long clkctr; 207 u64 clkctr;
270 volatile unsigned long long unused0; 208 u64 unused0;
271 volatile unsigned long long garbc; 209 u64 garbc;
272 volatile unsigned long long unused1; 210 u64 unused1;
273 volatile unsigned long long unused2; 211 u64 unused2;
274 volatile unsigned long long ramp; 212 u64 ramp;
275 volatile unsigned long long unused3; 213 u64 unused3;
276 volatile unsigned long long jmpadr; 214 u64 jmpadr;
277}; 215};
278 216
279#undef endian_def_l2 217#undef endian_def_l2
@@ -282,8 +220,6 @@ struct tx4938_ccfg_reg {
282#undef endian_def_b2s 220#undef endian_def_b2s
283#undef endian_def_b4 221#undef endian_def_b4
284 222
285#endif /* __ASSEMBLY__ */
286
287/* 223/*
288 * NDFMC 224 * NDFMC
289 */ 225 */
@@ -360,7 +296,7 @@ struct tx4938_ccfg_reg {
360#define TX4938_CCFG_BEOW 0x00010000 296#define TX4938_CCFG_BEOW 0x00010000
361#define TX4938_CCFG_WR 0x00008000 297#define TX4938_CCFG_WR 0x00008000
362#define TX4938_CCFG_TOE 0x00004000 298#define TX4938_CCFG_TOE 0x00004000
363#define TX4938_CCFG_PCIXARB 0x00002000 299#define TX4938_CCFG_PCIARB 0x00002000
364#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 300#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
365#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) 301#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
366#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) 302#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
@@ -436,110 +372,6 @@ struct tx4938_ccfg_reg {
436#define TX4938_CLKCTR_SIO0RST 0x00000002 372#define TX4938_CLKCTR_SIO0RST 0x00000002
437#define TX4938_CLKCTR_SIO1RST 0x00000001 373#define TX4938_CLKCTR_SIO1RST 0x00000001
438 374
439/* bits for G2PSTATUS/G2PMASK */
440#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003
441#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002
442#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001
443
444/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
445#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900
446
447/* bits for PBACFG */
448#define TX4938_PCIC_PBACFG_FIXPA 0x00000008
449#define TX4938_PCIC_PBACFG_RPBA 0x00000004
450#define TX4938_PCIC_PBACFG_PBAEN 0x00000002
451#define TX4938_PCIC_PBACFG_BMCEN 0x00000001
452
453/* bits for G2PMnGBASE */
454#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
455#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
456
457/* bits for G2PIOGBASE */
458#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
459#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
460
461/* bits for PCICSTATUS/PCICMASK */
462#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8
463#define TX4938_PCIC_PCICSTATUS_PME 0x00000400
464#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200
465#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100
466#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080
467#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020
468#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010
469#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008
470#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002
471#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001
472
473/* bits for PCICCFG */
474#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
475#define TX4938_PCIC_PCICCFG_HRST 0x00000800
476#define TX4938_PCIC_PCICCFG_SRST 0x00000400
477#define TX4938_PCIC_PCICCFG_IRBER 0x00000200
478#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
479#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100
480#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080
481#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040
482#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020
483#define TX4938_PCIC_PCICCFG_TCAR 0x00000010
484#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008
485
486/* bits for P2GMnGBASE */
487#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
488#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
489#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
490
491/* bits for P2GIOGBASE */
492#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
493#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
494#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
495
496#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
497#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
498
499/* bits for PDMCFG */
500#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000
501#define TX4938_PCIC_PDMCFG_EXFER 0x00100000
502#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800
503#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
504#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11)
505#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11)
506#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11)
507#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11)
508#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11)
509#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11)
510#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
511#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400
512#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200
513#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100
514#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080
515#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040
516#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020
517#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
518#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
519#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
520#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
521#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002
522#define TX4938_PCIC_PDMCFG_CHRST 0x00000001
523
524/* bits for PDMSTS */
525#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
526#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
527#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
528#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000
529#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800
530#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400
531#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200
532#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100
533#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080
534#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040
535#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020
536#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008
537#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004
538#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002
539#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001
540#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0
541#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f
542
543/* 375/*
544 * DMA 376 * DMA
545 */ 377 */
@@ -595,15 +427,15 @@ struct tx4938_ccfg_reg {
595#define TX4938_DMA_CSR_DESERR 0x00000002 427#define TX4938_DMA_CSR_DESERR 0x00000002
596#define TX4938_DMA_CSR_SORERR 0x00000001 428#define TX4938_DMA_CSR_SORERR 0x00000001
597 429
598#ifndef __ASSEMBLY__
599
600#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 430#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
601#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 431#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
602#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) 432#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
603#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) 433#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
604#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 434#define tx4938_pcicptr tx4927_pcicptr
605#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 435#define tx4938_pcic1ptr \
606#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 436 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
437#define tx4938_ccfgptr \
438 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
607#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) 439#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
608#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) 440#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
609#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 441#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
@@ -611,17 +443,25 @@ struct tx4938_ccfg_reg {
611#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) 443#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
612 444
613 445
614#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) 446#define TX4938_REV_PCODE() \
615#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) 447 ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
448
449#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
450#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
451#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
616 452
617#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) 453#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
618#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) 454#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
619 455
456#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)])
620#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) 457#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
621#define TX4938_EBUSC_SIZE(ch) \ 458#define TX4938_EBUSC_SIZE(ch) \
622 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) 459 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
623 460
624 461int tx4938_report_pciclk(void);
625#endif /* !__ASSEMBLY__ */ 462void tx4938_report_pci1clk(void);
463int tx4938_pciclk66_setup(void);
464struct pci_dev;
465int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
626 466
627#endif 467#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 17:27:26 -0400