diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2008-07-18 12:51:47 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-20 09:38:21 -0400 |
commit | 94a4c32939dede9328c6e4face335eb8441fc18d (patch) | |
tree | 0ac510bf3b90cb79fe94112b95dd77d96c190bf9 /include/asm-mips/txx9/tx4927.h | |
parent | 255033a9bb900a06c9a7798908ce12557d24fb66 (diff) |
[MIPS] TXx9: Add 64-bit support
SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but
actually it was broken for long time (or from the beginning). Now it
should work.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/txx9/tx4927.h')
-rw-r--r-- | include/asm-mips/txx9/tx4927.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index c9212155f686..ceb4b79ff4e3 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h | |||
@@ -46,15 +46,22 @@ | |||
46 | #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) | 46 | #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) |
47 | #define TX4927_NR_TMR 3 | 47 | #define TX4927_NR_TMR 3 |
48 | #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) | 48 | #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) |
49 | #define TX4927_NR_SIO 2 | ||
50 | #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) | ||
51 | #define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) | ||
49 | 52 | ||
50 | #define TX4927_IR_INT(n) (2 + (n)) | 53 | #define TX4927_IR_INT(n) (2 + (n)) |
51 | #define TX4927_IR_SIO(n) (8 + (n)) | 54 | #define TX4927_IR_SIO(n) (8 + (n)) |
52 | #define TX4927_IR_PCIC 16 | 55 | #define TX4927_IR_PCIC 16 |
56 | #define TX4927_NUM_IR_TMR 3 | ||
57 | #define TX4927_IR_TMR(n) (17 + (n)) | ||
53 | #define TX4927_IR_PCIERR 22 | 58 | #define TX4927_IR_PCIERR 22 |
54 | #define TX4927_NUM_IR 32 | 59 | #define TX4927_NUM_IR 32 |
55 | 60 | ||
56 | #define TX4927_IRC_INT 2 /* IP[2] in Status register */ | 61 | #define TX4927_IRC_INT 2 /* IP[2] in Status register */ |
57 | 62 | ||
63 | #define TX4927_NUM_PIO 16 | ||
64 | |||
58 | struct tx4927_sdramc_reg { | 65 | struct tx4927_sdramc_reg { |
59 | u64 cr[4]; | 66 | u64 cr[4]; |
60 | u64 unused0[4]; | 67 | u64 unused0[4]; |
@@ -175,6 +182,10 @@ struct tx4927_ccfg_reg { | |||
175 | ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) | 182 | ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) |
176 | #define tx4927_ebuscptr \ | 183 | #define tx4927_ebuscptr \ |
177 | ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) | 184 | ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) |
185 | #define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG) | ||
186 | |||
187 | #define TX4927_REV_PCODE() \ | ||
188 | ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16) | ||
178 | 189 | ||
179 | #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) | 190 | #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) |
180 | #define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) | 191 | #define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) |
@@ -232,6 +243,10 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new) | |||
232 | } | 243 | } |
233 | 244 | ||
234 | unsigned int tx4927_get_mem_size(void); | 245 | unsigned int tx4927_get_mem_size(void); |
246 | void tx4927_wdr_init(void); | ||
247 | void tx4927_setup(void); | ||
248 | void tx4927_time_init(unsigned int tmrnr); | ||
249 | void tx4927_setup_serial(void); | ||
235 | int tx4927_report_pciclk(void); | 250 | int tx4927_report_pciclk(void); |
236 | int tx4927_pciclk66_setup(void); | 251 | int tx4927_pciclk66_setup(void); |
237 | void tx4927_irq_init(void); | 252 | void tx4927_irq_init(void); |