[PATCH] mips: nuke trailing whitespace

Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
author: Ralf Baechle <ralf@linux-mips.org> 2005-09-03 18:56:17 -0400
committer: Linus Torvalds <torvalds@evo.osdl.org> 2005-09-05 03:06:07 -0400
commit: 42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch)
tree: 332370ff3889fabb66a45fb5dcf605b142de77c8 /include/asm-mips/tx4927/tx4927.h
parent: 875d43e72b5bf22161a81de7554f88eccf8a51ae (diff)
1 files changed, 26 insertions, 26 deletions
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 5d939db6e220..3bb7f0087d68 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -45,14 +45,14 @@
 /* TX4927 SDRAM controller (64-bit registers) */
-#define TX4927_SDRAMC_BASE              0x8000 
+#define TX4927_SDRAMC_BASE              0x8000
-#define TX4927_SDRAMC_SDCCR0            0x8000 
+#define TX4927_SDRAMC_SDCCR0            0x8000
 #define TX4927_SDRAMC_SDCCR1            0x8008
 #define TX4927_SDRAMC_SDCCR2            0x8010
 #define TX4927_SDRAMC_SDCCR3            0x8018
 #define TX4927_SDRAMC_SDCTR             0x8040
 #define TX4927_SDRAMC_SDCMD             0x8058
-#define TX4927_SDRAMC_LIMIT             0x8fff 
+#define TX4927_SDRAMC_LIMIT             0x8fff
 /* TX4927 external bus controller (64-bit registers) */
@@ -289,8 +289,8 @@
 /* TX4927 serial port 0 (32-bit registers) */
-#define TX4927_SIO0_BASE                         0xf300 
+#define TX4927_SIO0_BASE                         0xf300
-#define TX4927_SIO0_SILCR0                       0xf300 
+#define TX4927_SIO0_SILCR0                       0xf300
 #define TX4927_SIO0_SILCR0_RESERVED_16_31                BM_16_31
 #define TX4927_SIO0_SILCR0_RWUB                          BM_15_15
 #define TX4927_SIO0_SILCR0_TWUB                          BM_14_14
@@ -309,7 +309,7 @@
 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT            (~BM_00_01)
 #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC           BM_01_01
 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC           BM_00_01
-#define TX4927_SIO0_SIDICR0                      0xf304 
+#define TX4927_SIO0_SIDICR0                      0xf304
 #define TX4927_SIO0_SIDICR0_RESERVED_16_31               BM_16_31
 #define TX4927_SIO0_SIDICR0_TDE                          BM_15_15
 #define TX4927_SIO0_SIDICR0_RDE                          BM_14_14
@@ -330,7 +330,7 @@
 #define TX4927_SIO0_SIDICR0_STIE_TRDY                    BM_02_02
 #define TX4927_SIO0_SIDICR0_STIE_TXALS                   BM_01_01
 #define TX4927_SIO0_SIDICR0_STIE_UBRKD                   BM_00_00
-#define TX4927_SIO0_SIDISR0                      0xf308 
+#define TX4927_SIO0_SIDISR0                      0xf308
 #define TX4927_SIO0_SIDISR0_RESERVED_16_31               BM_16_31
 #define TX4927_SIO0_SIDISR0_UBRK                         BM_15_15
 #define TX4927_SIO0_SIDISR0_UVALID                       BM_14_14
@@ -344,7 +344,7 @@
 #define TX4927_SIO0_SIDISR0_STIS                         BM_06_06
 #define TX4927_SIO0_SIDISR0_RESERVED_05_05               BM_05_05
 #define TX4927_SIO0_SIDISR0_RFDN                         BM_00_04
-#define TX4927_SIO0_SISCISR0                     0xf30c 
+#define TX4927_SIO0_SISCISR0                     0xf30c
 #define TX4927_SIO0_SISCISR0_RESERVED_06_31              BM_06_31
 #define TX4927_SIO0_SISCISR0_OERS                        BM_05_05
 #define TX4927_SIO0_SISCISR0_CTSS                        BM_04_04
@@ -352,7 +352,7 @@
 #define TX4927_SIO0_SISCISR0_TRDY                        BM_02_02
 #define TX4927_SIO0_SISCISR0_TXALS                       BM_01_01
 #define TX4927_SIO0_SISCISR0_UBRKD                       BM_00_00
-#define TX4927_SIO0_SIFCR0                       0xf310 
+#define TX4927_SIO0_SIFCR0                       0xf310
 #define TX4927_SIO0_SIFCR0_RESERVED_16_31                BM_16_31
 #define TX4927_SIO0_SIFCR0_SWRST                         BM_16_31
 #define TX4927_SIO0_SIFCR0_RESERVED_09_14                BM_09_14
@@ -370,7 +370,7 @@
 #define TX4927_SIO0_SIFCR0_TFRST                         BM_02_02
 #define TX4927_SIO0_SIFCR0_RFRST                         BM_01_01
 #define TX4927_SIO0_SIFCR0_FRSTE                         BM_00_00
-#define TX4927_SIO0_SIFLCR0                      0xf314 
+#define TX4927_SIO0_SIFLCR0                      0xf314
 #define TX4927_SIO0_SIFLCR0_RESERVED_13_31               BM_13_31
 #define TX4927_SIO0_SIFLCR0_RCS                          BM_12_12
 #define TX4927_SIO0_SIFLCR0_TES                          BM_11_11
@@ -381,7 +381,7 @@
 #define TX4927_SIO0_SIFLCR0_RESERVED_05_06               BM_05_06
 #define TX4927_SIO0_SIFLCR0_RTSTL                        BM_01_04
 #define TX4927_SIO0_SIFLCR0_TBRK                         BM_00_00
-#define TX4927_SIO0_SIBGR0                       0xf318 
+#define TX4927_SIO0_SIBGR0                       0xf318
 #define TX4927_SIO0_SIBGR0_RESERVED_10_31                BM_10_31
 #define TX4927_SIO0_SIBGR0_BCLK                          BM_08_09
 #define TX4927_SIO0_SIBGR0_BCLK_T0                     (~BM_08_09)
@@ -389,28 +389,28 @@
 #define TX4927_SIO0_SIBGR0_BCLK_T4                       BM_09_09
 #define TX4927_SIO0_SIBGR0_BCLK_T6                       BM_08_09
 #define TX4927_SIO0_SIBGR0_BRD                           BM_00_07
-#define TX4927_SIO0_SITFIF00                     0xf31c 
+#define TX4927_SIO0_SITFIF00                     0xf31c
 #define TX4927_SIO0_SITFIF00_RESERVED_08_31              BM_08_31
 #define TX4927_SIO0_SITFIF00_TXD                         BM_00_07
-#define TX4927_SIO0_SIRFIFO0                     0xf320          
+#define TX4927_SIO0_SIRFIFO0                     0xf320
 #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31              BM_08_31
 #define TX4927_SIO0_SIRFIFO0_RXD                         BM_00_07
-#define TX4927_SIO0_SIRFIFO0                     0xf320          
+#define TX4927_SIO0_SIRFIFO0                     0xf320
-#define TX4927_SIO0_LIMIT                        0xf3ff 
+#define TX4927_SIO0_LIMIT                        0xf3ff
 /* TX4927 serial port 1 (32-bit registers) */
-#define TX4927_SIO1_BASE                0xf400 
+#define TX4927_SIO1_BASE                0xf400
-#define TX4927_SIO1_SILCR1              0xf400 
+#define TX4927_SIO1_SILCR1              0xf400
-#define TX4927_SIO1_SIDICR1             0xf404 
+#define TX4927_SIO1_SIDICR1             0xf404
-#define TX4927_SIO1_SIDISR1             0xf408 
+#define TX4927_SIO1_SIDISR1             0xf408
-#define TX4927_SIO1_SISCISR1            0xf40c 
+#define TX4927_SIO1_SISCISR1            0xf40c
-#define TX4927_SIO1_SIFCR1              0xf410 
+#define TX4927_SIO1_SIFCR1              0xf410
-#define TX4927_SIO1_SIFLCR1             0xf414 
+#define TX4927_SIO1_SIFLCR1             0xf414
-#define TX4927_SIO1_SIBGR1              0xf418 
+#define TX4927_SIO1_SIBGR1              0xf418
-#define TX4927_SIO1_SITFIF01            0xf41c 
+#define TX4927_SIO1_SITFIF01            0xf41c
-#define TX4927_SIO1_SIRFIFO1            0xf420 
+#define TX4927_SIO1_SIRFIFO1            0xf420
-#define TX4927_SIO1_LIMIT               0xf4ff 
+#define TX4927_SIO1_LIMIT               0xf4ff
 /* TX4927 parallel port (32-bit registers) */
author	Ralf Baechle <ralf@linux-mips.org>	2005-09-03 18:56:17 -0400
committer	Linus Torvalds <torvalds@evo.osdl.org>	2005-09-05 03:06:07 -0400
commit	42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch)
tree	332370ff3889fabb66a45fb5dcf605b142de77c8 /include/asm-mips/tx4927/tx4927.h
parent	875d43e72b5bf22161a81de7554f88eccf8a51ae (diff)

diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 5d939db6e220..3bb7f0087d68 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h
@@ -45,14 +45,14 @@
45		45
46		46
47	/* TX4927 SDRAM controller (64-bit registers) */	47	/* TX4927 SDRAM controller (64-bit registers) */
48	#define TX4927_SDRAMC_BASE 0x8000	48	#define TX4927_SDRAMC_BASE 0x8000
49	#define TX4927_SDRAMC_SDCCR0 0x8000	49	#define TX4927_SDRAMC_SDCCR0 0x8000
50	#define TX4927_SDRAMC_SDCCR1 0x8008	50	#define TX4927_SDRAMC_SDCCR1 0x8008
51	#define TX4927_SDRAMC_SDCCR2 0x8010	51	#define TX4927_SDRAMC_SDCCR2 0x8010
52	#define TX4927_SDRAMC_SDCCR3 0x8018	52	#define TX4927_SDRAMC_SDCCR3 0x8018
53	#define TX4927_SDRAMC_SDCTR 0x8040	53	#define TX4927_SDRAMC_SDCTR 0x8040
54	#define TX4927_SDRAMC_SDCMD 0x8058	54	#define TX4927_SDRAMC_SDCMD 0x8058
55	#define TX4927_SDRAMC_LIMIT 0x8fff	55	#define TX4927_SDRAMC_LIMIT 0x8fff
56		56
57		57
58	/* TX4927 external bus controller (64-bit registers) */	58	/* TX4927 external bus controller (64-bit registers) */
@@ -289,8 +289,8 @@
289		289
290		290
291	/* TX4927 serial port 0 (32-bit registers) */	291	/* TX4927 serial port 0 (32-bit registers) */
292	#define TX4927_SIO0_BASE 0xf300	292	#define TX4927_SIO0_BASE 0xf300
293	#define TX4927_SIO0_SILCR0 0xf300	293	#define TX4927_SIO0_SILCR0 0xf300
294	#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31	294	#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31
295	#define TX4927_SIO0_SILCR0_RWUB BM_15_15	295	#define TX4927_SIO0_SILCR0_RWUB BM_15_15
296	#define TX4927_SIO0_SILCR0_TWUB BM_14_14	296	#define TX4927_SIO0_SILCR0_TWUB BM_14_14
@@ -309,7 +309,7 @@
309	#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)	309	#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)
310	#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01	310	#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01
311	#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01	311	#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01
312	#define TX4927_SIO0_SIDICR0 0xf304	312	#define TX4927_SIO0_SIDICR0 0xf304
313	#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31	313	#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31
314	#define TX4927_SIO0_SIDICR0_TDE BM_15_15	314	#define TX4927_SIO0_SIDICR0_TDE BM_15_15
315	#define TX4927_SIO0_SIDICR0_RDE BM_14_14	315	#define TX4927_SIO0_SIDICR0_RDE BM_14_14
@@ -330,7 +330,7 @@
330	#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02	330	#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02
331	#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01	331	#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01
332	#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00	332	#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00
333	#define TX4927_SIO0_SIDISR0 0xf308	333	#define TX4927_SIO0_SIDISR0 0xf308
334	#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31	334	#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31
335	#define TX4927_SIO0_SIDISR0_UBRK BM_15_15	335	#define TX4927_SIO0_SIDISR0_UBRK BM_15_15
336	#define TX4927_SIO0_SIDISR0_UVALID BM_14_14	336	#define TX4927_SIO0_SIDISR0_UVALID BM_14_14
@@ -344,7 +344,7 @@
344	#define TX4927_SIO0_SIDISR0_STIS BM_06_06	344	#define TX4927_SIO0_SIDISR0_STIS BM_06_06
345	#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05	345	#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05
346	#define TX4927_SIO0_SIDISR0_RFDN BM_00_04	346	#define TX4927_SIO0_SIDISR0_RFDN BM_00_04
347	#define TX4927_SIO0_SISCISR0 0xf30c	347	#define TX4927_SIO0_SISCISR0 0xf30c
348	#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31	348	#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31
349	#define TX4927_SIO0_SISCISR0_OERS BM_05_05	349	#define TX4927_SIO0_SISCISR0_OERS BM_05_05
350	#define TX4927_SIO0_SISCISR0_CTSS BM_04_04	350	#define TX4927_SIO0_SISCISR0_CTSS BM_04_04
@@ -352,7 +352,7 @@
352	#define TX4927_SIO0_SISCISR0_TRDY BM_02_02	352	#define TX4927_SIO0_SISCISR0_TRDY BM_02_02
353	#define TX4927_SIO0_SISCISR0_TXALS BM_01_01	353	#define TX4927_SIO0_SISCISR0_TXALS BM_01_01
354	#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00	354	#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00
355	#define TX4927_SIO0_SIFCR0 0xf310	355	#define TX4927_SIO0_SIFCR0 0xf310
356	#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31	356	#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31
357	#define TX4927_SIO0_SIFCR0_SWRST BM_16_31	357	#define TX4927_SIO0_SIFCR0_SWRST BM_16_31
358	#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14	358	#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14
@@ -370,7 +370,7 @@
370	#define TX4927_SIO0_SIFCR0_TFRST BM_02_02	370	#define TX4927_SIO0_SIFCR0_TFRST BM_02_02
371	#define TX4927_SIO0_SIFCR0_RFRST BM_01_01	371	#define TX4927_SIO0_SIFCR0_RFRST BM_01_01
372	#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00	372	#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00
373	#define TX4927_SIO0_SIFLCR0 0xf314	373	#define TX4927_SIO0_SIFLCR0 0xf314
374	#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31	374	#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31
375	#define TX4927_SIO0_SIFLCR0_RCS BM_12_12	375	#define TX4927_SIO0_SIFLCR0_RCS BM_12_12
376	#define TX4927_SIO0_SIFLCR0_TES BM_11_11	376	#define TX4927_SIO0_SIFLCR0_TES BM_11_11
@@ -381,7 +381,7 @@
381	#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06	381	#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06
382	#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04	382	#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04
383	#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00	383	#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00
384	#define TX4927_SIO0_SIBGR0 0xf318	384	#define TX4927_SIO0_SIBGR0 0xf318
385	#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31	385	#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31
386	#define TX4927_SIO0_SIBGR0_BCLK BM_08_09	386	#define TX4927_SIO0_SIBGR0_BCLK BM_08_09
387	#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)	387	#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)
@@ -389,28 +389,28 @@
389	#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09	389	#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09
390	#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09	390	#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09
391	#define TX4927_SIO0_SIBGR0_BRD BM_00_07	391	#define TX4927_SIO0_SIBGR0_BRD BM_00_07
392	#define TX4927_SIO0_SITFIF00 0xf31c	392	#define TX4927_SIO0_SITFIF00 0xf31c
393	#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31	393	#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31
394	#define TX4927_SIO0_SITFIF00_TXD BM_00_07	394	#define TX4927_SIO0_SITFIF00_TXD BM_00_07
395	#define TX4927_SIO0_SIRFIFO0 0xf320	395	#define TX4927_SIO0_SIRFIFO0 0xf320
396	#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31	396	#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31
397	#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07	397	#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07
398	#define TX4927_SIO0_SIRFIFO0 0xf320	398	#define TX4927_SIO0_SIRFIFO0 0xf320
399	#define TX4927_SIO0_LIMIT 0xf3ff	399	#define TX4927_SIO0_LIMIT 0xf3ff
400		400
401		401
402	/* TX4927 serial port 1 (32-bit registers) */	402	/* TX4927 serial port 1 (32-bit registers) */
403	#define TX4927_SIO1_BASE 0xf400	403	#define TX4927_SIO1_BASE 0xf400
404	#define TX4927_SIO1_SILCR1 0xf400	404	#define TX4927_SIO1_SILCR1 0xf400
405	#define TX4927_SIO1_SIDICR1 0xf404	405	#define TX4927_SIO1_SIDICR1 0xf404
406	#define TX4927_SIO1_SIDISR1 0xf408	406	#define TX4927_SIO1_SIDISR1 0xf408
407	#define TX4927_SIO1_SISCISR1 0xf40c	407	#define TX4927_SIO1_SISCISR1 0xf40c
408	#define TX4927_SIO1_SIFCR1 0xf410	408	#define TX4927_SIO1_SIFCR1 0xf410
409	#define TX4927_SIO1_SIFLCR1 0xf414	409	#define TX4927_SIO1_SIFLCR1 0xf414
410	#define TX4927_SIO1_SIBGR1 0xf418	410	#define TX4927_SIO1_SIBGR1 0xf418
411	#define TX4927_SIO1_SITFIF01 0xf41c	411	#define TX4927_SIO1_SITFIF01 0xf41c
412	#define TX4927_SIO1_SIRFIFO1 0xf420	412	#define TX4927_SIO1_SIRFIFO1 0xf420
413	#define TX4927_SIO1_LIMIT 0xf4ff	413	#define TX4927_SIO1_LIMIT 0xf4ff
414		414
415		415
416	/* TX4927 parallel port (32-bit registers) */	416	/* TX4927 parallel port (32-bit registers) */