diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
commit | 21a151d8ca3aa74ee79f9791a9d4dc370d3e0636 (patch) | |
tree | 8556b3a32ded6a49225beb4a7aa4447cc87a0e00 /include/asm-mips/sibyte/sb1250_uart.h | |
parent | 49a89efbbbcc178a39555c43bd59a7593c429664 (diff) |
[MIPS] checkfiles: Fix "need space after that ','" errors.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/sibyte/sb1250_uart.h')
-rw-r--r-- | include/asm-mips/sibyte/sb1250_uart.h | 70 |
1 files changed, 35 insertions, 35 deletions
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index cf74fedcbef1..d835bf280140 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h | |||
@@ -46,8 +46,8 @@ | |||
46 | */ | 46 | */ |
47 | 47 | ||
48 | #define S_DUART_BITS_PER_CHAR 0 | 48 | #define S_DUART_BITS_PER_CHAR 0 |
49 | #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) | 49 | #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) |
50 | #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) | 50 | #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) |
51 | 51 | ||
52 | #define K_DUART_BITS_PER_CHAR_RSV0 0 | 52 | #define K_DUART_BITS_PER_CHAR_RSV0 0 |
53 | #define K_DUART_BITS_PER_CHAR_RSV1 1 | 53 | #define K_DUART_BITS_PER_CHAR_RSV1 1 |
@@ -64,8 +64,8 @@ | |||
64 | #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) | 64 | #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) |
65 | 65 | ||
66 | #define S_DUART_PARITY_MODE 3 | 66 | #define S_DUART_PARITY_MODE 3 |
67 | #define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) | 67 | #define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) |
68 | #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) | 68 | #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) |
69 | 69 | ||
70 | #define K_DUART_PARITY_MODE_ADD 0 | 70 | #define K_DUART_PARITY_MODE_ADD 0 |
71 | #define K_DUART_PARITY_MODE_ADD_FIXED 1 | 71 | #define K_DUART_PARITY_MODE_ADD_FIXED 1 |
@@ -89,7 +89,7 @@ | |||
89 | * Register: DUART_MODE_REG_2_B | 89 | * Register: DUART_MODE_REG_2_B |
90 | */ | 90 | */ |
91 | 91 | ||
92 | #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ | 92 | #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ |
93 | 93 | ||
94 | #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) | 94 | #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) |
95 | #define M_DUART_STOP_BIT_LEN_1 0 | 95 | #define M_DUART_STOP_BIT_LEN_1 0 |
@@ -100,8 +100,8 @@ | |||
100 | #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ | 100 | #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ |
101 | 101 | ||
102 | #define S_DUART_CHAN_MODE 6 | 102 | #define S_DUART_CHAN_MODE 6 |
103 | #define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) | 103 | #define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) |
104 | #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) | 104 | #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) |
105 | 105 | ||
106 | #define K_DUART_CHAN_MODE_NORMAL 0 | 106 | #define K_DUART_CHAN_MODE_NORMAL 0 |
107 | #define K_DUART_CHAN_MODE_LCL_LOOP 2 | 107 | #define K_DUART_CHAN_MODE_LCL_LOOP 2 |
@@ -123,8 +123,8 @@ | |||
123 | #define M_DUART_TX_DIS _SB_MAKEMASK1(3) | 123 | #define M_DUART_TX_DIS _SB_MAKEMASK1(3) |
124 | 124 | ||
125 | #define S_DUART_MISC_CMD 4 | 125 | #define S_DUART_MISC_CMD 4 |
126 | #define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) | 126 | #define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) |
127 | #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) | 127 | #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) |
128 | 128 | ||
129 | #define K_DUART_MISC_CMD_NOACTION0 0 | 129 | #define K_DUART_MISC_CMD_NOACTION0 0 |
130 | #define K_DUART_MISC_CMD_NOACTION1 1 | 130 | #define K_DUART_MISC_CMD_NOACTION1 1 |
@@ -168,7 +168,7 @@ | |||
168 | * Register: DUART_CLK_SEL_B | 168 | * Register: DUART_CLK_SEL_B |
169 | */ | 169 | */ |
170 | 170 | ||
171 | #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) | 171 | #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) |
172 | #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) | 172 | #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) |
173 | 173 | ||
174 | /* | 174 | /* |
@@ -179,8 +179,8 @@ | |||
179 | * Register: DUART_TX_HOLD_B | 179 | * Register: DUART_TX_HOLD_B |
180 | */ | 180 | */ |
181 | 181 | ||
182 | #define M_DUART_RX_DATA _SB_MAKEMASK(8,0) | 182 | #define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) |
183 | #define M_DUART_TX_DATA _SB_MAKEMASK(8,0) | 183 | #define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) |
184 | 184 | ||
185 | /* | 185 | /* |
186 | * DUART Input Port Register (Table 10-10) | 186 | * DUART Input Port Register (Table 10-10) |
@@ -202,10 +202,10 @@ | |||
202 | */ | 202 | */ |
203 | 203 | ||
204 | #define S_DUART_IN_PIN_VAL 0 | 204 | #define S_DUART_IN_PIN_VAL 0 |
205 | #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) | 205 | #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) |
206 | 206 | ||
207 | #define S_DUART_IN_PIN_CHNG 4 | 207 | #define S_DUART_IN_PIN_CHNG 4 |
208 | #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) | 208 | #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) |
209 | 209 | ||
210 | 210 | ||
211 | /* | 211 | /* |
@@ -217,7 +217,7 @@ | |||
217 | #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) | 217 | #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) |
218 | #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ | 218 | #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ |
219 | #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) | 219 | #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) |
220 | #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ | 220 | #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ |
221 | 221 | ||
222 | /* | 222 | /* |
223 | * DUART Aux Control Register (Table 10-15) | 223 | * DUART Aux Control Register (Table 10-15) |
@@ -228,7 +228,7 @@ | |||
228 | #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) | 228 | #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) |
229 | #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) | 229 | #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) |
230 | #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) | 230 | #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) |
231 | #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) | 231 | #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) |
232 | 232 | ||
233 | #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) | 233 | #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) |
234 | #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) | 234 | #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) |
@@ -242,18 +242,18 @@ | |||
242 | 242 | ||
243 | #define S_DUART_ISR_RX_A 1 | 243 | #define S_DUART_ISR_RX_A 1 |
244 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) | 244 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) |
245 | #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) | 245 | #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) |
246 | #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) | 246 | #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) |
247 | 247 | ||
248 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) | 248 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) |
249 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) | 249 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) |
250 | #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) | 250 | #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) |
251 | 251 | ||
252 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) | 252 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) |
253 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) | 253 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) |
254 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) | 254 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) |
255 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) | 255 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) |
256 | #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) | 256 | #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) |
257 | 257 | ||
258 | /* | 258 | /* |
259 | * DUART Channel A Interrupt Status Register (Table 10-17) | 259 | * DUART Channel A Interrupt Status Register (Table 10-17) |
@@ -266,8 +266,8 @@ | |||
266 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) | 266 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) |
267 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) | 267 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) |
268 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) | 268 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) |
269 | #define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) | 269 | #define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) |
270 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) | 270 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) |
271 | 271 | ||
272 | /* | 272 | /* |
273 | * DUART Interrupt Mask Register (Table 10-19) | 273 | * DUART Interrupt Mask Register (Table 10-19) |
@@ -278,13 +278,13 @@ | |||
278 | #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) | 278 | #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) |
279 | #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) | 279 | #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) |
280 | #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) | 280 | #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) |
281 | #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) | 281 | #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) |
282 | 282 | ||
283 | #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) | 283 | #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) |
284 | #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) | 284 | #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) |
285 | #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) | 285 | #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) |
286 | #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) | 286 | #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) |
287 | #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) | 287 | #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) |
288 | 288 | ||
289 | /* | 289 | /* |
290 | * DUART Channel A Interrupt Mask Register (Table 10-20) | 290 | * DUART Channel A Interrupt Mask Register (Table 10-20) |
@@ -297,8 +297,8 @@ | |||
297 | #define M_DUART_IMR_RX _SB_MAKEMASK1(1) | 297 | #define M_DUART_IMR_RX _SB_MAKEMASK1(1) |
298 | #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) | 298 | #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) |
299 | #define M_DUART_IMR_IN _SB_MAKEMASK1(3) | 299 | #define M_DUART_IMR_IN _SB_MAKEMASK1(3) |
300 | #define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) | 300 | #define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) |
301 | #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) | 301 | #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) |
302 | 302 | ||
303 | 303 | ||
304 | /* | 304 | /* |
@@ -310,7 +310,7 @@ | |||
310 | #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) | 310 | #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) |
311 | #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) | 311 | #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) |
312 | #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) | 312 | #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) |
313 | #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) | 313 | #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) |
314 | 314 | ||
315 | /* | 315 | /* |
316 | * DUART Output Port Clear Register (Table 10-23) | 316 | * DUART Output Port Clear Register (Table 10-23) |
@@ -321,7 +321,7 @@ | |||
321 | #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) | 321 | #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) |
322 | #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) | 322 | #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) |
323 | #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) | 323 | #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) |
324 | #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) | 324 | #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) |
325 | 325 | ||
326 | /* | 326 | /* |
327 | * DUART Output Port RTS Register (Table 10-24) | 327 | * DUART Output Port RTS Register (Table 10-24) |
@@ -332,7 +332,7 @@ | |||
332 | #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) | 332 | #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) |
333 | #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) | 333 | #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) |
334 | #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) | 334 | #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) |
335 | #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) | 335 | #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) |
336 | 336 | ||
337 | #define M_DUART_OUT_PIN_SET(chan) \ | 337 | #define M_DUART_OUT_PIN_SET(chan) \ |
338 | (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) | 338 | (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) |
@@ -345,14 +345,14 @@ | |||
345 | */ | 345 | */ |
346 | 346 | ||
347 | #define S_DUART_SIG_FULL _SB_MAKE64(0) | 347 | #define S_DUART_SIG_FULL _SB_MAKE64(0) |
348 | #define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) | 348 | #define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) |
349 | #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) | 349 | #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) |
350 | #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) | 350 | #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) |
351 | 351 | ||
352 | #define S_DUART_INT_TIME _SB_MAKE64(4) | 352 | #define S_DUART_INT_TIME _SB_MAKE64(4) |
353 | #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) | 353 | #define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) |
354 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) | 354 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) |
355 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) | 355 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) |
356 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | 356 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
357 | 357 | ||
358 | 358 | ||