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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /include/asm-mips/mips-boards
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mips-boards')
-rw-r--r--include/asm-mips/mips-boards/bonito64.h436
-rw-r--r--include/asm-mips/mips-boards/generic.h104
-rw-r--r--include/asm-mips/mips-boards/launch.h35
-rw-r--r--include/asm-mips/mips-boards/malta.h102
-rw-r--r--include/asm-mips/mips-boards/maltaint.h110
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h258
-rw-r--r--include/asm-mips/mips-boards/piix4.h80
-rw-r--r--include/asm-mips/mips-boards/prom.h47
-rw-r--r--include/asm-mips/mips-boards/sim.h40
-rw-r--r--include/asm-mips/mips-boards/simint.h31
10 files changed, 0 insertions, 1243 deletions
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
deleted file mode 100644
index a0f04bb99c99..000000000000
--- a/include/asm-mips/mips-boards/bonito64.h
+++ /dev/null
@@ -1,436 +0,0 @@
1/*
2 * Bonito Register Map
3 *
4 * This file is the original bonito.h from Algorithmics with minor changes
5 * to fit into linux.
6 *
7 * Copyright (c) 1999 Algorithmics Ltd
8 *
9 * Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved.
11 *
12 * Algorithmics gives permission for anyone to use and modify this file
13 * without any obligation or license condition except that you retain
14 * this copyright message in any source redistribution in whole or part.
15 *
16 */
17
18/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
19/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
20
21#ifndef _ASM_MIPS_BOARDS_BONITO64_H
22#define _ASM_MIPS_BOARDS_BONITO64_H
23
24#ifdef __ASSEMBLY__
25
26/* offsets from base register */
27#define BONITO(x) (x)
28
29#elif defined(CONFIG_LEMOTE_FULONG)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else
35
36/*
37 * Algorithmics Bonito64 system controller register base.
38 */
39extern unsigned long _pcictrl_bonito;
40extern unsigned long _pcictrl_bonito_pcicfg;
41
42#define BONITO(x) *(volatile u32 *)(_pcictrl_bonito + (x))
43
44#endif /* __ASSEMBLY__ */
45
46
47#define BONITO_BOOT_BASE 0x1fc00000
48#define BONITO_BOOT_SIZE 0x00100000
49#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
50#define BONITO_FLASH_BASE 0x1c000000
51#define BONITO_FLASH_SIZE 0x03000000
52#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
53#define BONITO_SOCKET_BASE 0x1f800000
54#define BONITO_SOCKET_SIZE 0x00400000
55#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
56#define BONITO_REG_BASE 0x1fe00000
57#define BONITO_REG_SIZE 0x00040000
58#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
59#define BONITO_DEV_BASE 0x1ff00000
60#define BONITO_DEV_SIZE 0x00100000
61#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
62#define BONITO_PCILO_BASE 0x10000000
63#define BONITO_PCILO_SIZE 0x0c000000
64#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
65#define BONITO_PCILO0_BASE 0x10000000
66#define BONITO_PCILO1_BASE 0x14000000
67#define BONITO_PCILO2_BASE 0x18000000
68#define BONITO_PCIHI_BASE 0x20000000
69#define BONITO_PCIHI_SIZE 0x20000000
70#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
71#define BONITO_PCIIO_BASE 0x1fd00000
72#define BONITO_PCIIO_SIZE 0x00100000
73#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
74#define BONITO_PCICFG_BASE 0x1fe80000
75#define BONITO_PCICFG_SIZE 0x00080000
76#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
77
78
79/* Bonito Register Bases */
80
81#define BONITO_PCICONFIGBASE 0x00
82#define BONITO_REGBASE 0x100
83
84
85/* PCI Configuration Registers */
86
87#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x))
88#define BONITO_PCIDID BONITO_PCI_REG(0x00)
89#define BONITO_PCICMD BONITO_PCI_REG(0x04)
90#define BONITO_PCICLASS BONITO_PCI_REG(0x08)
91#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c)
92#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10)
93#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14)
94#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18)
95#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30)
96#define BONITO_PCIINT BONITO_PCI_REG(0x3c)
97
98#define BONITO_PCICMD_PERR_CLR 0x80000000
99#define BONITO_PCICMD_SERR_CLR 0x40000000
100#define BONITO_PCICMD_MABORT_CLR 0x20000000
101#define BONITO_PCICMD_MTABORT_CLR 0x10000000
102#define BONITO_PCICMD_TABORT_CLR 0x08000000
103#define BONITO_PCICMD_MPERR_CLR 0x01000000
104#define BONITO_PCICMD_PERRRESPEN 0x00000040
105#define BONITO_PCICMD_ASTEPEN 0x00000080
106#define BONITO_PCICMD_SERREN 0x00000100
107#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00
108#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8
109
110
111
112
113/* 1. Bonito h/w Configuration */
114/* Power on register */
115
116#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00)
117
118#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000
119#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000
120#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000
121#define BONITO_BONPONCFG_CPUBIGEND 0x00004000
122/* Added by RPF 11-9-00 */
123#define BONITO_BONPONCFG_BURSTORDER 0x00001000
124/* --- */
125#define BONITO_BONPONCFG_CPUPARITY 0x00002000
126#define BONITO_BONPONCFG_CPUTYPE 0x00000007
127#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0
128#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008
129#define BONITO_BONPONCFG_IS_ARBITER 0x00000010
130#define BONITO_BONPONCFG_ROMBOOT 0x000000c0
131#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6
132
133#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
134#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
135#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
136#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
137
138#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100
139#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200
140#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400
141#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800
142#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020
143
144
145/* Other Bonito configuration */
146
147#define BONITO_BONGENCFG_OFFSET 0x4
148#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
149
150#define BONITO_BONGENCFG_DEBUGMODE 0x00000001
151#define BONITO_BONGENCFG_SNOOPEN 0x00000002
152#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004
153
154#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008
155#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010
156#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
157#define BONITO_BONGENCFG_BYTESWAP 0x00000040
158
159#define BONITO_BONGENCFG_UNCACHED 0x00000080
160#define BONITO_BONGENCFG_PREFETCHEN 0x00000100
161#define BONITO_BONGENCFG_WBEHINDEN 0x00000200
162#define BONITO_BONGENCFG_CACHEALG 0x00000c00
163#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
164#define BONITO_BONGENCFG_PCIQUEUE 0x00001000
165#define BONITO_BONGENCFG_CACHESTOP 0x00002000
166#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000
167#define BONITO_BONGENCFG_BUSERREN 0x00008000
168#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
169#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000
170
171/* 2. IO & IDE configuration */
172
173#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08)
174
175/* 3. IO & IDE configuration */
176
177#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c)
178
179/* 4. PCI address map control */
180
181#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10)
182#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14)
183#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18)
184
185/* 5. ICU & GPIO regs */
186
187/* GPIO Regs - r/w */
188
189#define BONITO_GPIODATA_OFFSET 0x1c
190#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
191#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20)
192
193/* ICU Configuration Regs - r/w */
194
195#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24)
196#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28)
197#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c)
198
199/* ICU Enable Regs - IntEn & IntISR are r/o. */
200
201#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30)
202#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34)
203#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38)
204#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c)
205
206/* PCI mail boxes */
207
208#define BONITO_PCIMAIL0_OFFSET 0x40
209#define BONITO_PCIMAIL1_OFFSET 0x44
210#define BONITO_PCIMAIL2_OFFSET 0x48
211#define BONITO_PCIMAIL3_OFFSET 0x4c
212#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40)
213#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44)
214#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48)
215#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c)
216
217
218/* 6. PCI cache */
219
220#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50)
221#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54)
222
223#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58)
224#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c)
225
226
227/*
228#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60)
229#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64)
230*/
231
232/* 7. IDE DMA & Copier */
233
234#define BONITO_CONFIGBASE 0x000
235#define BONITO_BONITOBASE 0x100
236#define BONITO_LDMABASE 0x200
237#define BONITO_COPBASE 0x300
238#define BONITO_REG_BLOCKMASK 0x300
239
240#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0)
241#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0)
242#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4)
243#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8)
244#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc)
245
246#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0)
247#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0)
248#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4)
249#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8)
250#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc)
251
252
253/* ###### Bit Definitions for individual Registers #### */
254
255/* Gen DMA. */
256
257#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc
258#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2
259#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc
260#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2
261#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe
262#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
263#define BONITO_IDECOPGO_DMA_WRITE 0x00010000
264#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000
265#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
266
267#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
268#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000
269
270/* DRAM - sdCfg */
271
272#define BONITO_SDCFG_AROWBITS 0x00000003
273#define BONITO_SDCFG_AROWBITS_SHIFT 0
274#define BONITO_SDCFG_ACOLBITS 0x0000000c
275#define BONITO_SDCFG_ACOLBITS_SHIFT 2
276#define BONITO_SDCFG_ABANKBIT 0x00000010
277#define BONITO_SDCFG_ASIDES 0x00000020
278#define BONITO_SDCFG_AABSENT 0x00000040
279#define BONITO_SDCFG_AWIDTH64 0x00000080
280
281#define BONITO_SDCFG_BROWBITS 0x00000300
282#define BONITO_SDCFG_BROWBITS_SHIFT 8
283#define BONITO_SDCFG_BCOLBITS 0x00000c00
284#define BONITO_SDCFG_BCOLBITS_SHIFT 10
285#define BONITO_SDCFG_BBANKBIT 0x00001000
286#define BONITO_SDCFG_BSIDES 0x00002000
287#define BONITO_SDCFG_BABSENT 0x00004000
288#define BONITO_SDCFG_BWIDTH64 0x00008000
289
290#define BONITO_SDCFG_EXTRDDATA 0x00010000
291#define BONITO_SDCFG_EXTRASCAS 0x00020000
292#define BONITO_SDCFG_EXTPRECH 0x00040000
293#define BONITO_SDCFG_EXTRASWIDTH 0x00180000
294#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19
295/* Changed by RPF 11-9-00 */
296#define BONITO_SDCFG_DRAMMODESET 0x00200000
297/* --- */
298#define BONITO_SDCFG_DRAMEXTREGS 0x00400000
299#define BONITO_SDCFG_DRAMPARITY 0x00800000
300/* Added by RPF 11-9-00 */
301#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000
302#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
303#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000
304/* --- */
305
306/* PCI Cache - pciCacheCtrl */
307
308#define BONITO_PCICACHECTRL_CACHECMD 0x00000007
309#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0
310#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018
311#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3
312#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020
313
314#define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100
315#define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200
316#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
317#define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800
318
319#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001
320#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002
321#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004
322
323#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008
324#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010
325#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020
326
327#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040
328#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080
329#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100
330
331#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200
332#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400
333#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800
334
335#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000
336#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000
337#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
338#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000
339#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000
340#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
341#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000
342#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21
343#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000
344/* Added by RPF 11-9-00 */
345#define BONITO_IODEVCFG_CPUCLOCKPERIOD 0xfc000000
346#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
347/* --- */
348
349/* gpio */
350#define BONITO_GPIO_GPIOW 0x000003ff
351#define BONITO_GPIO_GPIOW_SHIFT 0
352#define BONITO_GPIO_GPIOR 0x01ff0000
353#define BONITO_GPIO_GPIOR_SHIFT 16
354#define BONITO_GPIO_GPINR 0xfe000000
355#define BONITO_GPIO_GPINR_SHIFT 25
356#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
357#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
358#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
359
360/* ICU */
361#define BONITO_ICU_MBOXES 0x0000000f
362#define BONITO_ICU_MBOXES_SHIFT 0
363#define BONITO_ICU_DMARDY 0x00000010
364#define BONITO_ICU_DMAEMPTY 0x00000020
365#define BONITO_ICU_COPYRDY 0x00000040
366#define BONITO_ICU_COPYEMPTY 0x00000080
367#define BONITO_ICU_COPYERR 0x00000100
368#define BONITO_ICU_PCIIRQ 0x00000200
369#define BONITO_ICU_MASTERERR 0x00000400
370#define BONITO_ICU_SYSTEMERR 0x00000800
371#define BONITO_ICU_DRAMPERR 0x00001000
372#define BONITO_ICU_RETRYERR 0x00002000
373#define BONITO_ICU_GPIOS 0x01ff0000
374#define BONITO_ICU_GPIOS_SHIFT 16
375#define BONITO_ICU_GPINS 0x7e000000
376#define BONITO_ICU_GPINS_SHIFT 25
377#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
378#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
379#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
380
381/* pcimap */
382
383#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f
384#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0
385#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0
386#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6
387#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
388#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
389#define BONITO_PCIMAP_PCIMAP_2 0x00040000
390#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
391
392#define BONITO_PCIMAP_WINSIZE (1<<26)
393#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
394#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26)
395
396/* pcimembaseCfg */
397
398#define BONITO_PCIMEMBASECFG_MASK 0xf0000000
399#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f
400#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0
401#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0
402#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5
403#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400
404#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800
405
406#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000
407#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12
408#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000
409#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17
410#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000
411#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000
412
413#define BONITO_PCIMEMBASECFG_ASHIFT 23
414#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
415#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
416#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
417
418#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
419
420
421#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
422#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
423#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
424
425#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \
426 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
427 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
428 )
429
430/* PCICmd */
431
432#define BONITO_PCICMD_MEMEN 0x00000002
433#define BONITO_PCICMD_MSTREN 0x00000004
434
435
436#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
deleted file mode 100644
index 7f0b034dd9a5..000000000000
--- a/include/asm-mips/mips-boards/generic.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Defines of the MIPS boards specific address-MAP, registers, etc.
19 */
20#ifndef __ASM_MIPS_BOARDS_GENERIC_H
21#define __ASM_MIPS_BOARDS_GENERIC_H
22
23#include <asm/addrspace.h>
24#include <asm/byteorder.h>
25#include <asm/mips-boards/bonito64.h>
26
27/*
28 * Display register base.
29 */
30#define ASCII_DISPLAY_WORD_BASE 0x1f000410
31#define ASCII_DISPLAY_POS_BASE 0x1f000418
32
33
34/*
35 * Yamon Prom print address.
36 */
37#define YAMON_PROM_PRINT_ADDR 0x1fc00504
38
39
40/*
41 * Reset register.
42 */
43#define SOFTRES_REG 0x1f000500
44#define GORESET 0x42
45
46/*
47 * Revision register.
48 */
49#define MIPS_REVISION_REG 0x1fc00010
50#define MIPS_REVISION_CORID_QED_RM5261 0
51#define MIPS_REVISION_CORID_CORE_LV 1
52#define MIPS_REVISION_CORID_BONITO64 2
53#define MIPS_REVISION_CORID_CORE_20K 3
54#define MIPS_REVISION_CORID_CORE_FPGA 4
55#define MIPS_REVISION_CORID_CORE_MSC 5
56#define MIPS_REVISION_CORID_CORE_EMUL 6
57#define MIPS_REVISION_CORID_CORE_FPGA2 7
58#define MIPS_REVISION_CORID_CORE_FPGAR2 8
59#define MIPS_REVISION_CORID_CORE_FPGA3 9
60#define MIPS_REVISION_CORID_CORE_24K 10
61#define MIPS_REVISION_CORID_CORE_FPGA4 11
62#define MIPS_REVISION_CORID_CORE_FPGA5 12
63
64/**** Artificial corid defines ****/
65/*
66 * CoreEMUL with Bonito System Controller is treated like a Core20K
67 * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
68 */
69#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
70#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
71
72#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
73
74extern int mips_revision_corid;
75
76#define MIPS_REVISION_SCON_OTHER 0
77#define MIPS_REVISION_SCON_SOCITSC 1
78#define MIPS_REVISION_SCON_SOCITSCP 2
79
80/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
81#define MIPS_REVISION_SCON_UNKNOWN -1
82#define MIPS_REVISION_SCON_GT64120 -2
83#define MIPS_REVISION_SCON_BONITO -3
84#define MIPS_REVISION_SCON_BRTL -4
85#define MIPS_REVISION_SCON_SOCIT -5
86#define MIPS_REVISION_SCON_ROCIT -6
87
88#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
89
90extern int mips_revision_sconid;
91
92extern void mips_reboot_setup(void);
93
94#ifdef CONFIG_PCI
95extern void mips_pcibios_init(void);
96#else
97#define mips_pcibios_init() do { } while (0)
98#endif
99
100#ifdef CONFIG_KGDB
101extern void kgdb_config(void);
102#endif
103
104#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h
deleted file mode 100644
index d8ae7f95a522..000000000000
--- a/include/asm-mips/mips-boards/launch.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 *
3 */
4
5#ifndef _ASSEMBLER_
6
7struct cpulaunch {
8 unsigned long pc;
9 unsigned long gp;
10 unsigned long sp;
11 unsigned long a0;
12 unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */
13 unsigned long flags;
14};
15
16#else
17
18#define LOG2CPULAUNCH 5
19#define LAUNCH_PC 0
20#define LAUNCH_GP 4
21#define LAUNCH_SP 8
22#define LAUNCH_A0 12
23#define LAUNCH_FLAGS 28
24
25#endif
26
27#define LAUNCH_FREADY 1
28#define LAUNCH_FGO 2
29#define LAUNCH_FGONE 4
30
31#define CPULAUNCH 0x00000f00
32#define NCPULAUNCH 8
33
34/* Polling period in count cycles for secondary CPU's */
35#define LAUNCHPERIOD 10000
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
deleted file mode 100644
index c1891578fa65..000000000000
--- a/include/asm-mips/mips-boards/malta.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Defines of the Malta board specific address-MAP, registers, etc.
19 */
20#ifndef __ASM_MIPS_BOARDS_MALTA_H
21#define __ASM_MIPS_BOARDS_MALTA_H
22
23#include <asm/addrspace.h>
24#include <asm/io.h>
25#include <asm/mips-boards/msc01_pci.h>
26#include <asm/gt64120.h>
27
28/* Mips interrupt controller found in SOCit variations */
29#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
30#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
31
32/*
33 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
34 * Bonito system controllers.
35 */
36#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
37#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
38#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
39
40static inline unsigned long get_gt_port_base(unsigned long reg)
41{
42 unsigned long addr;
43 addr = GT_READ(reg);
44 return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
45}
46
47static inline unsigned long get_msc_port_base(unsigned long reg)
48{
49 unsigned long addr;
50 MSC_READ(reg, addr);
51 return (unsigned long) ioremap(addr, 0x10000);
52}
53
54/*
55 * GCMP Specific definitions
56 */
57#define GCMP_BASE_ADDR 0x1fbf8000
58#define GCMP_ADDRSPACE_SZ (256 * 1024)
59
60/*
61 * GIC Specific definitions
62 */
63#define GIC_BASE_ADDR 0x1bdc0000
64#define GIC_ADDRSPACE_SZ (128 * 1024)
65
66/*
67 * MSC01 BIU Specific definitions
68 * FIXME : These should be elsewhere ?
69 */
70#define MSC01_BIU_REG_BASE 0x1bc80000
71#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
72#define MSC01_SC_CFG_OFS 0x0110
73#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
74#define MSC01_SC_CFG_GICPRES_SHF 2
75#define MSC01_SC_CFG_GICENA_SHF 3
76
77/*
78 * Malta RTC-device indirect register access.
79 */
80#define MALTA_RTC_ADR_REG 0x70
81#define MALTA_RTC_DAT_REG 0x71
82
83/*
84 * Malta SMSC FDC37M817 Super I/O Controller register.
85 */
86#define SMSC_CONFIG_REG 0x3f0
87#define SMSC_DATA_REG 0x3f1
88
89#define SMSC_CONFIG_DEVNUM 0x7
90#define SMSC_CONFIG_ACTIVATE 0x30
91#define SMSC_CONFIG_ENTER 0x55
92#define SMSC_CONFIG_EXIT 0xaa
93
94#define SMSC_CONFIG_DEVNUM_FLOPPY 0
95
96#define SMSC_CONFIG_ACTIVATE_ENABLE 1
97
98#define SMSC_WRITE(x, a) outb(x, a)
99
100#define MALTA_JMPRS_REG 0x1f000210
101
102#endif /* __ASM_MIPS_BOARDS_MALTA_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
deleted file mode 100644
index cea872fc6f5c..000000000000
--- a/include/asm-mips/mips-boards/maltaint.h
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Defines for the Malta interrupt controller.
23 *
24 */
25#ifndef _MIPS_MALTAINT_H
26#define _MIPS_MALTAINT_H
27
28#include <irq.h>
29
30/*
31 * Interrupts 0..15 are used for Malta ISA compatible interrupts
32 */
33#define MALTA_INT_BASE 0
34
35/* CPU interrupt offsets */
36#define MIPSCPU_INT_SW0 0
37#define MIPSCPU_INT_SW1 1
38#define MIPSCPU_INT_MB0 2
39#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
40#define MIPSCPU_INT_MB1 3
41#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
42#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
43#define MIPSCPU_INT_MB2 4
44#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
45#define MIPSCPU_INT_MB3 5
46#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
47#define MIPSCPU_INT_MB4 6
48#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
49
50/*
51 * Interrupts 64..127 are used for Soc-it Classic interrupts
52 */
53#define MSC01C_INT_BASE 64
54
55/* SOC-it Classic interrupt offsets */
56#define MSC01C_INT_TMR 0
57#define MSC01C_INT_PCI 1
58
59/*
60 * Interrupts 64..127 are used for Soc-it EIC interrupts
61 */
62#define MSC01E_INT_BASE 64
63
64/* SOC-it EIC interrupt offsets */
65#define MSC01E_INT_SW0 1
66#define MSC01E_INT_SW1 2
67#define MSC01E_INT_MB0 3
68#define MSC01E_INT_I8259A MSC01E_INT_MB0
69#define MSC01E_INT_MB1 4
70#define MSC01E_INT_SMI MSC01E_INT_MB1
71#define MSC01E_INT_MB2 5
72#define MSC01E_INT_MB3 6
73#define MSC01E_INT_COREHI MSC01E_INT_MB3
74#define MSC01E_INT_MB4 7
75#define MSC01E_INT_CORELO MSC01E_INT_MB4
76#define MSC01E_INT_TMR 8
77#define MSC01E_INT_PCI 9
78#define MSC01E_INT_PERFCTR 10
79#define MSC01E_INT_CPUCTR 11
80
81/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
82#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
83#define GIC_CPU_INT1 1 /* . */
84#define GIC_CPU_INT2 2 /* . */
85#define GIC_CPU_INT3 3 /* . */
86#define GIC_CPU_INT4 4 /* . */
87#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
88
89#define GIC_EXT_INTR(x) x
90
91/* Dummy data */
92#define X 0xdead
93
94/* External Interrupts used for IPI */
95#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16
96#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
97#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
98#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
99#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
100#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
101#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
102#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
103
104#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
105
106#ifndef __ASSEMBLY__
107extern void maltaint_init(void);
108#endif
109
110#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
deleted file mode 100644
index e036b7dd6deb..000000000000
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * PCI Register definitions for the MIPS System Controller.
3 *
4 * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved.
5 * Authors: Carsten Langgaard <carstenl@mips.com>
6 * Maciej W. Rozycki <macro@mips.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
13#define __ASM_MIPS_BOARDS_MSC01_PCI_H
14
15/*
16 * Register offset addresses
17 */
18
19#define MSC01_PCI_ID_OFS 0x0000
20#define MSC01_PCI_SC2PMBASL_OFS 0x0208
21#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
22#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
23#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
24#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
25#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
26#define MSC01_PCI_P2SCMSKL_OFS 0x0308
27#define MSC01_PCI_P2SCMAPL_OFS 0x0318
28#define MSC01_PCI_INTCFG_OFS 0x0600
29#define MSC01_PCI_INTSTAT_OFS 0x0608
30#define MSC01_PCI_CFGADDR_OFS 0x0610
31#define MSC01_PCI_CFGDATA_OFS 0x0618
32#define MSC01_PCI_IACK_OFS 0x0620
33#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
34#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
35#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
36#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
37#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
38#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
39#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
40#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
41#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
42#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
43#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
44#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
45#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
46#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
47#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
48#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
49#define MSC01_PCI_BAR0_OFS 0x2220
50#define MSC01_PCI_CFG_OFS 0x2380
51#define MSC01_PCI_SWAP_OFS 0x2388
52
53
54/*****************************************************************************
55 * Register encodings
56 ****************************************************************************/
57
58#define MSC01_PCI_ID_ID_SHF 16
59#define MSC01_PCI_ID_ID_MSK 0x00ff0000
60#define MSC01_PCI_ID_ID_HOSTBRIDGE 82
61#define MSC01_PCI_ID_MAR_SHF 8
62#define MSC01_PCI_ID_MAR_MSK 0x0000ff00
63#define MSC01_PCI_ID_MIR_SHF 0
64#define MSC01_PCI_ID_MIR_MSK 0x000000ff
65
66#define MSC01_PCI_SC2PMBASL_BAS_SHF 24
67#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000
68
69#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24
70#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
71
72#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24
73#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000
74
75#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24
76#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000
77
78#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24
79#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
80
81#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24
82#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000
83
84#define MSC01_PCI_P2SCMSKL_MSK_SHF 24
85#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000
86
87#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
88#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
89
90#define MSC01_PCI_INTCFG_RST_SHF 10
91#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
92#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
93#define MSC01_PCI_INTCFG_MWE_SHF 9
94#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
95#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
96#define MSC01_PCI_INTCFG_DTO_SHF 8
97#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
98#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
99#define MSC01_PCI_INTCFG_MA_SHF 7
100#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
101#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
102#define MSC01_PCI_INTCFG_TA_SHF 6
103#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
104#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
105#define MSC01_PCI_INTCFG_RTY_SHF 5
106#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
107#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
108#define MSC01_PCI_INTCFG_MWP_SHF 4
109#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
110#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
111#define MSC01_PCI_INTCFG_MRP_SHF 3
112#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
113#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
114#define MSC01_PCI_INTCFG_SWP_SHF 2
115#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
116#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
117#define MSC01_PCI_INTCFG_SRP_SHF 1
118#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
119#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
120#define MSC01_PCI_INTCFG_SE_SHF 0
121#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
122#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
123
124#define MSC01_PCI_INTSTAT_RST_SHF 10
125#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
126#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
127#define MSC01_PCI_INTSTAT_MWE_SHF 9
128#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
129#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
130#define MSC01_PCI_INTSTAT_DTO_SHF 8
131#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
132#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
133#define MSC01_PCI_INTSTAT_MA_SHF 7
134#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
135#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
136#define MSC01_PCI_INTSTAT_TA_SHF 6
137#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
138#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
139#define MSC01_PCI_INTSTAT_RTY_SHF 5
140#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
141#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
142#define MSC01_PCI_INTSTAT_MWP_SHF 4
143#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
144#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
145#define MSC01_PCI_INTSTAT_MRP_SHF 3
146#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
147#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
148#define MSC01_PCI_INTSTAT_SWP_SHF 2
149#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
150#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
151#define MSC01_PCI_INTSTAT_SRP_SHF 1
152#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
153#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
154#define MSC01_PCI_INTSTAT_SE_SHF 0
155#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
156#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
157
158#define MSC01_PCI_CFGADDR_BNUM_SHF 16
159#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
160#define MSC01_PCI_CFGADDR_DNUM_SHF 11
161#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800
162#define MSC01_PCI_CFGADDR_FNUM_SHF 8
163#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700
164#define MSC01_PCI_CFGADDR_RNUM_SHF 2
165#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc
166
167#define MSC01_PCI_CFGDATA_DATA_SHF 0
168#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
169
170/* The defines below are ONLY valid for a MEM bar! */
171#define MSC01_PCI_BAR0_SIZE_SHF 4
172#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
173#define MSC01_PCI_BAR0_P_SHF 3
174#define MSC01_PCI_BAR0_P_MSK 0x00000008
175#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
176#define MSC01_PCI_BAR0_D_SHF 1
177#define MSC01_PCI_BAR0_D_MSK 0x00000006
178#define MSC01_PCI_BAR0_T_SHF 0
179#define MSC01_PCI_BAR0_T_MSK 0x00000001
180#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
181
182
183#define MSC01_PCI_CFG_RA_SHF 17
184#define MSC01_PCI_CFG_RA_MSK 0x00020000
185#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
186#define MSC01_PCI_CFG_G_SHF 16
187#define MSC01_PCI_CFG_G_MSK 0x00010000
188#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
189#define MSC01_PCI_CFG_EN_SHF 15
190#define MSC01_PCI_CFG_EN_MSK 0x00008000
191#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
192#define MSC01_PCI_CFG_MAXRTRY_SHF 0
193#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
194
195#define MSC01_PCI_SWAP_IO_SHF 18
196#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
197#define MSC01_PCI_SWAP_MEM_SHF 16
198#define MSC01_PCI_SWAP_MEM_MSK 0x00030000
199#define MSC01_PCI_SWAP_BAR0_SHF 0
200#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003
201#define MSC01_PCI_SWAP_NOSWAP 0
202#define MSC01_PCI_SWAP_BYTESWAP 1
203
204/*
205 * MIPS System controller PCI register base.
206 *
207 * FIXME - are these macros specific to Malta and co or to the MSC? If the
208 * latter, they should be moved elsewhere.
209 */
210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
211#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000
212
213extern unsigned long _pcictrl_msc;
214
215#define MSC01_PCI_REG_BASE _pcictrl_msc
216
217#define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
218#define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
219
220/*
221 * Registers absolute addresses
222 */
223
224#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
225#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
226#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
227#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
228#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
229#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
230#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
231#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
232#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
233#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
234#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
235#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
236#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
237#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
238#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
239#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
240#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
241#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
242#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
243#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
244#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
245#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
246#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
247#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
248#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
249#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
250#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
251#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
252#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
253#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
254#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
255#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
256#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
257
258#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */
diff --git a/include/asm-mips/mips-boards/piix4.h b/include/asm-mips/mips-boards/piix4.h
deleted file mode 100644
index 2971d60f2e95..000000000000
--- a/include/asm-mips/mips-boards/piix4.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Register definitions for Intel PIIX4 South Bridge Device.
19 */
20#ifndef __ASM_MIPS_BOARDS_PIIX4_H
21#define __ASM_MIPS_BOARDS_PIIX4_H
22
23/************************************************************************
24 * IO register offsets
25 ************************************************************************/
26#define PIIX4_ICTLR1_ICW1 0x20
27#define PIIX4_ICTLR1_ICW2 0x21
28#define PIIX4_ICTLR1_ICW3 0x21
29#define PIIX4_ICTLR1_ICW4 0x21
30#define PIIX4_ICTLR2_ICW1 0xa0
31#define PIIX4_ICTLR2_ICW2 0xa1
32#define PIIX4_ICTLR2_ICW3 0xa1
33#define PIIX4_ICTLR2_ICW4 0xa1
34#define PIIX4_ICTLR1_OCW1 0x21
35#define PIIX4_ICTLR1_OCW2 0x20
36#define PIIX4_ICTLR1_OCW3 0x20
37#define PIIX4_ICTLR1_OCW4 0x20
38#define PIIX4_ICTLR2_OCW1 0xa1
39#define PIIX4_ICTLR2_OCW2 0xa0
40#define PIIX4_ICTLR2_OCW3 0xa0
41#define PIIX4_ICTLR2_OCW4 0xa0
42
43
44/************************************************************************
45 * Register encodings.
46 ************************************************************************/
47#define PIIX4_OCW2_NSEOI (0x1 << 5)
48#define PIIX4_OCW2_SEOI (0x3 << 5)
49#define PIIX4_OCW2_RNSEOI (0x5 << 5)
50#define PIIX4_OCW2_RAEOIS (0x4 << 5)
51#define PIIX4_OCW2_RAEOIC (0x0 << 5)
52#define PIIX4_OCW2_RSEOI (0x7 << 5)
53#define PIIX4_OCW2_SP (0x6 << 5)
54#define PIIX4_OCW2_NOP (0x2 << 5)
55
56#define PIIX4_OCW2_SEL (0x0 << 3)
57
58#define PIIX4_OCW2_ILS_0 0
59#define PIIX4_OCW2_ILS_1 1
60#define PIIX4_OCW2_ILS_2 2
61#define PIIX4_OCW2_ILS_3 3
62#define PIIX4_OCW2_ILS_4 4
63#define PIIX4_OCW2_ILS_5 5
64#define PIIX4_OCW2_ILS_6 6
65#define PIIX4_OCW2_ILS_7 7
66#define PIIX4_OCW2_ILS_8 0
67#define PIIX4_OCW2_ILS_9 1
68#define PIIX4_OCW2_ILS_10 2
69#define PIIX4_OCW2_ILS_11 3
70#define PIIX4_OCW2_ILS_12 4
71#define PIIX4_OCW2_ILS_13 5
72#define PIIX4_OCW2_ILS_14 6
73#define PIIX4_OCW2_ILS_15 7
74
75#define PIIX4_OCW3_SEL (0x1 << 3)
76
77#define PIIX4_OCW3_IRR 0x2
78#define PIIX4_OCW3_ISR 0x3
79
80#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h
deleted file mode 100644
index a9db576a9768..000000000000
--- a/include/asm-mips/mips-boards/prom.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * MIPS boards bootprom interface for the Linux kernel.
23 *
24 */
25
26#ifndef _MIPS_PROM_H
27#define _MIPS_PROM_H
28
29extern char *prom_getcmdline(void);
30extern char *prom_getenv(char *name);
31extern void prom_init_cmdline(void);
32extern void prom_meminit(void);
33extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
34extern void mips_display_message(const char *str);
35extern void mips_display_word(unsigned int num);
36extern void mips_scroll_message(void);
37extern int get_ethernet_addr(char *ethernet_addr);
38
39/* Memory descriptor management. */
40#define PROM_MAX_PMEMBLOCKS 32
41struct prom_pmemblock {
42 unsigned long base; /* Within KSEG0. */
43 unsigned int size; /* In bytes. */
44 unsigned int type; /* free or prom memory */
45};
46
47#endif /* !(_MIPS_PROM_H) */
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
deleted file mode 100644
index acb7c2331d98..000000000000
--- a/include/asm-mips/mips-boards/sim.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#ifndef _ASM_MIPS_BOARDS_SIM_H
20#define _ASM_MIPS_BOARDS_SIM_H
21
22#define STATS_ON 1
23#define STATS_OFF 2
24#define STATS_CLEAR 3
25#define STATS_DUMP 4
26#define TRACE_ON 5
27#define TRACE_OFF 6
28
29
30#define simcfg(code) \
31({ \
32 __asm__ __volatile__( \
33 "sltiu $0,$0, %0" \
34 ::"i"(code) \
35 ); \
36})
37
38
39
40#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
deleted file mode 100644
index 8ef6db76d5c1..000000000000
--- a/include/asm-mips/mips-boards/simint.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */
17#ifndef _MIPS_SIMINT_H
18#define _MIPS_SIMINT_H
19
20#include <irq.h>
21
22#define SIM_INT_BASE 0
23#define MIPSCPU_INT_MB0 2
24#define MIPS_CPU_TIMER_IRQ 7
25
26
27#define MSC01E_INT_BASE 64
28
29#define MSC01E_INT_CPUCTR 11
30
31#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 08:43:36 -0500