[MIPS] Pb1200/DBAu1200: move platform code to its proper place

Since both the IDE interface and SMC 91C111 Ethernet chip are on-board
devices, not SOC devices, move the platform device registration form the
common to the board specific code.

While at it, remove semicolon (which didn't break compilation only by
chance) from the AU1XXX_ATA_DDMA_REQ macro and do some renaming:

- change 'au1200_ide0_' variable name prefix to the mere 'ide_';

- change 'smc91x_' variable name prefix to 'smc91c111_' since that's the
  name of the chip used on the boards;

- drop 'AU1XXX_' prefix from the names of macros describing IDE and Ethernet
  on-board devices;

- change 'SMC91111_' to 'SMC91C111_', change 'IRQ' to 'INT' in the names of
  the macros describing the Ethernet chip for consistency with the IDE
  macros;

- change 'ATA_' to 'IDE_' and 'OFFSET' to 'SHIFT' (since this value is
  indeed a shift count) in the names of the macros describing the IDE
  interface.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 9 insertions, 9 deletions

diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index edaa489b58f1..e2c6bcac3b42 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -182,15 +182,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define SET_VCC_VPP(VCC, VPP, SLOT)\
         ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 
-#define AU1XXX_SMC91111_PHYS_ADDR       (0x0D000300)
-#define AU1XXX_SMC91111_IRQ                     PB1200_ETH_INT
-
-#define AU1XXX_ATA_PHYS_ADDR            (0x0C800000)
-#define AU1XXX_ATA_REG_OFFSET           (5)
-#define AU1XXX_ATA_PHYS_LEN             (16 << AU1XXX_ATA_REG_OFFSET)
-#define AU1XXX_ATA_INT                  PB1200_IDE_INT
-#define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
-#define AU1XXX_ATA_RQSIZE               128
+#define SMC91C111_PHYS_ADDR     0x0D000300
+#define SMC91C111_INT           PB1200_ETH_INT
+
+#define IDE_PHYS_ADDR           0x0C800000
+#define IDE_REG_SHIFT           5
+#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
+#define IDE_INT                 PB1200_IDE_INT
+#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
+#define IDE_RQSIZE              128
 
 #define NAND_PHYS_ADDR   0x1C000000