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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-mips/mach-ocelot3
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-mips/mach-ocelot3')
-rw-r--r--include/asm-mips/mach-ocelot3/cpu-feature-overrides.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7473512384bc
--- /dev/null
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -0,0 +1,48 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 MontaVista Software Inc.
7 * Author: Manish Lachwani, mlachwani@mvista.com
8 * Copyright (C) 2004 Ralf Baechle
9 */
10#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
11#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
12
13/*
14 * Momentum Ocelot-3 is based on Rm7900 processor which
15 * is based on the E9000 core.
16 */
17#define cpu_has_watch 1
18#define cpu_has_mips16 0
19#define cpu_has_divec 0
20#define cpu_has_vce 0
21#define cpu_has_cache_cdex_p 0
22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
24#define cpu_has_mcheck 0
25#define cpu_has_ejtag 0
26
27#define cpu_has_llsc 1
28#define cpu_has_vtag_icache 0
29#define cpu_has_dc_aliases 0
30#define cpu_has_ic_fills_f_dc 0
31#define cpu_icache_snoops_remote_store 0
32
33#define cpu_has_nofpuex 0
34#define cpu_has_64bits 1
35
36#define cpu_has_subset_pcaches 0
37
38#define cpu_dcache_line_size() 32
39#define cpu_icache_line_size() 32
40#define cpu_scache_line_size() 32
41
42/*
43 * On the RM9000 we need to ensure that I-cache lines being fetches only
44 * contain valid instructions are funny things will happen.
45 */
46#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
47
48#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */