diff options
author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2006-06-23 05:04:13 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-23 10:42:56 -0400 |
commit | f2c780c1fdbe5008c902c2d7e37242ac5e60f0b9 (patch) | |
tree | f2fb215610897e06812548986f3c37a6d6dc38ca /include/asm-mips/mach-au1x00 | |
parent | c52c17622e27876c2395f59cfe342497a399de41 (diff) |
[PATCH] Au1550/1200: add missing PSC #define's, make OSS driver use the proper ones
Add missing PSC #define's required for the drivers using PSC on DBAu1550
board (also fixing Au1550 PSC3 address) and all Au1200-based boards as
well. Make the OSS driver use the correct PSC definitions fo each board.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips/mach-au1x00')
-rw-r--r-- | include/asm-mips/mach-au1x00/au1xxx_psc.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h index 5c3e2a38ce12..d7cbacdd21fe 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h | |||
@@ -39,7 +39,12 @@ | |||
39 | #define PSC0_BASE_ADDR 0xb1a00000 | 39 | #define PSC0_BASE_ADDR 0xb1a00000 |
40 | #define PSC1_BASE_ADDR 0xb1b00000 | 40 | #define PSC1_BASE_ADDR 0xb1b00000 |
41 | #define PSC2_BASE_ADDR 0xb0a00000 | 41 | #define PSC2_BASE_ADDR 0xb0a00000 |
42 | #define PSC3_BASE_ADDR 0xb0d00000 | 42 | #define PSC3_BASE_ADDR 0xb0b00000 |
43 | #endif | ||
44 | |||
45 | #ifdef CONFIG_SOC_AU1200 | ||
46 | #define PSC0_BASE_ADDR 0xb1a00000 | ||
47 | #define PSC1_BASE_ADDR 0xb1b00000 | ||
43 | #endif | 48 | #endif |
44 | 49 | ||
45 | /* The PSC select and control registers are common to | 50 | /* The PSC select and control registers are common to |
@@ -227,6 +232,8 @@ typedef struct psc_i2s { | |||
227 | #define PSC_I2SCFG_DD_DISABLE (1 << 27) | 232 | #define PSC_I2SCFG_DD_DISABLE (1 << 27) |
228 | #define PSC_I2SCFG_DE_ENABLE (1 << 26) | 233 | #define PSC_I2SCFG_DE_ENABLE (1 << 26) |
229 | #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) | 234 | #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) |
235 | #define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) | ||
236 | #define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) | ||
230 | #define PSC_I2SCFG_WI (1 << 15) | 237 | #define PSC_I2SCFG_WI (1 << 15) |
231 | 238 | ||
232 | #define PSC_I2SCFG_DIV_MASK (3 << 13) | 239 | #define PSC_I2SCFG_DIV_MASK (3 << 13) |