aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips/ip32
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /include/asm-mips/ip32
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/ip32')
-rw-r--r--include/asm-mips/ip32/crime.h158
-rw-r--r--include/asm-mips/ip32/ip32_ints.h114
-rw-r--r--include/asm-mips/ip32/mace.h365
3 files changed, 0 insertions, 637 deletions
diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h
deleted file mode 100644
index 7c36b0e5b1c6..000000000000
--- a/include/asm-mips/ip32/crime.h
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
3 * Engine)
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 2000 Harald Koerfgen
10 */
11
12#ifndef __ASM_CRIME_H__
13#define __ASM_CRIME_H__
14
15/*
16 * Address map
17 */
18#define CRIME_BASE 0x14000000 /* physical */
19
20struct sgi_crime {
21 volatile unsigned long id;
22#define CRIME_ID_MASK 0xff
23#define CRIME_ID_IDBITS 0xf0
24#define CRIME_ID_IDVALUE 0xa0
25#define CRIME_ID_REV 0x0f
26#define CRIME_REV_PETTY 0x00
27#define CRIME_REV_11 0x11
28#define CRIME_REV_13 0x13
29#define CRIME_REV_14 0x14
30
31 volatile unsigned long control;
32#define CRIME_CONTROL_MASK 0x3fff
33#define CRIME_CONTROL_TRITON_SYSADC 0x2000
34#define CRIME_CONTROL_CRIME_SYSADC 0x1000
35#define CRIME_CONTROL_HARD_RESET 0x0800
36#define CRIME_CONTROL_SOFT_RESET 0x0400
37#define CRIME_CONTROL_DOG_ENA 0x0200
38#define CRIME_CONTROL_ENDIANESS 0x0100
39#define CRIME_CONTROL_ENDIAN_BIG 0x0100
40#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
41#define CRIME_CONTROL_CQUEUE_HWM 0x000f
42#define CRIME_CONTROL_CQUEUE_SHFT 0
43#define CRIME_CONTROL_WBUF_HWM 0x00f0
44#define CRIME_CONTROL_WBUF_SHFT 8
45
46 volatile unsigned long istat;
47 volatile unsigned long imask;
48 volatile unsigned long soft_int;
49 volatile unsigned long hard_int;
50#define MACE_VID_IN1_INT BIT(0)
51#define MACE_VID_IN2_INT BIT(1)
52#define MACE_VID_OUT_INT BIT(2)
53#define MACE_ETHERNET_INT BIT(3)
54#define MACE_SUPERIO_INT BIT(4)
55#define MACE_MISC_INT BIT(5)
56#define MACE_AUDIO_INT BIT(6)
57#define MACE_PCI_BRIDGE_INT BIT(7)
58#define MACEPCI_SCSI0_INT BIT(8)
59#define MACEPCI_SCSI1_INT BIT(9)
60#define MACEPCI_SLOT0_INT BIT(10)
61#define MACEPCI_SLOT1_INT BIT(11)
62#define MACEPCI_SLOT2_INT BIT(12)
63#define MACEPCI_SHARED0_INT BIT(13)
64#define MACEPCI_SHARED1_INT BIT(14)
65#define MACEPCI_SHARED2_INT BIT(15)
66#define CRIME_GBE0_INT BIT(16)
67#define CRIME_GBE1_INT BIT(17)
68#define CRIME_GBE2_INT BIT(18)
69#define CRIME_GBE3_INT BIT(19)
70#define CRIME_CPUERR_INT BIT(20)
71#define CRIME_MEMERR_INT BIT(21)
72#define CRIME_RE_EMPTY_E_INT BIT(22)
73#define CRIME_RE_FULL_E_INT BIT(23)
74#define CRIME_RE_IDLE_E_INT BIT(24)
75#define CRIME_RE_EMPTY_L_INT BIT(25)
76#define CRIME_RE_FULL_L_INT BIT(26)
77#define CRIME_RE_IDLE_L_INT BIT(27)
78#define CRIME_SOFT0_INT BIT(28)
79#define CRIME_SOFT1_INT BIT(29)
80#define CRIME_SOFT2_INT BIT(30)
81#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
82#define CRIME_VICE_INT BIT(31)
83/* Masks for deciding who handles the interrupt */
84#define CRIME_MACE_INT_MASK 0x8f
85#define CRIME_MACEISA_INT_MASK 0x70
86#define CRIME_MACEPCI_INT_MASK 0xff00
87#define CRIME_CRIME_INT_MASK 0xffff0000
88
89 volatile unsigned long watchdog;
90#define CRIME_DOG_POWER_ON_RESET 0x00010000
91#define CRIME_DOG_WARM_RESET 0x00080000
92#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
93#define CRIME_DOG_VALUE 0x00007fff
94
95 volatile unsigned long timer;
96#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
97#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
98
99 volatile unsigned long cpu_error_addr;
100#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
101
102 volatile unsigned long cpu_error_stat;
103#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */
104#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
105#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
106#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
107
108 unsigned long _pad0[54];
109
110 volatile unsigned long mc_ctrl;
111 volatile unsigned long bank_ctrl[8];
112#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */
113#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
114#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
115#define CRIME_MAXBANKS 8
116
117 volatile unsigned long mem_ref_counter;
118#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */
119
120 volatile unsigned long mem_error_stat;
121#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
122#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
123#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
124#define CRIME_MEM_ERROR_RE_ID 0x00007f00
125#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
126#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
127#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
128#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
129#define CRIME_MEM_ERROR_RESERVED 0x00080000
130#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
131#define CRIME_MEM_ERROR_HARD_ERR 0x00200000
132#define CRIME_MEM_ERROR_MULTIPLE 0x00400000
133#define CRIME_MEM_ERROR_ECC 0x01800000
134#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
135#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
136#define CRIME_MEM_ERROR_INV 0x0e000000
137#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
138#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
139#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
140
141 volatile unsigned long mem_error_addr;
142#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
143
144 volatile unsigned long mem_ecc_syn;
145#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
146
147 volatile unsigned long mem_ecc_chk;
148#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
149
150 volatile unsigned long mem_ecc_repl;
151#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
152};
153
154extern struct sgi_crime __iomem *crime;
155
156#define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */
157
158#endif /* __ASM_CRIME_H__ */
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
deleted file mode 100644
index 85bc5302bce0..000000000000
--- a/include/asm-mips/ip32/ip32_ints.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Harald Koerfgen
7 */
8
9#ifndef __ASM_IP32_INTS_H
10#define __ASM_IP32_INTS_H
11
12#include <asm/irq.h>
13
14/*
15 * This list reflects the assignment of interrupt numbers to
16 * interrupting events. Order is fairly irrelevant to handling
17 * priority. This differs from irix.
18 */
19
20enum ip32_irq_no {
21 /*
22 * CPU interrupts are 0 ... 7
23 */
24
25 CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
26
27 /*
28 * MACE
29 */
30 MACE_VID_IN1_IRQ = CRIME_IRQ_BASE,
31 MACE_VID_IN2_IRQ,
32 MACE_VID_OUT_IRQ,
33 MACE_ETHERNET_IRQ,
34 /* SUPERIO, MISC, and AUDIO are MACEISA */
35 __MACE_SUPERIO,
36 __MACE_MISC,
37 __MACE_AUDIO,
38 MACE_PCI_BRIDGE_IRQ,
39
40 /*
41 * MACEPCI
42 */
43 MACEPCI_SCSI0_IRQ,
44 MACEPCI_SCSI1_IRQ,
45 MACEPCI_SLOT0_IRQ,
46 MACEPCI_SLOT1_IRQ,
47 MACEPCI_SLOT2_IRQ,
48 MACEPCI_SHARED0_IRQ,
49 MACEPCI_SHARED1_IRQ,
50 MACEPCI_SHARED2_IRQ,
51
52 /*
53 * CRIME
54 */
55 CRIME_GBE0_IRQ,
56 CRIME_GBE1_IRQ,
57 CRIME_GBE2_IRQ,
58 CRIME_GBE3_IRQ,
59 CRIME_CPUERR_IRQ,
60 CRIME_MEMERR_IRQ,
61 CRIME_RE_EMPTY_E_IRQ,
62 CRIME_RE_FULL_E_IRQ,
63 CRIME_RE_IDLE_E_IRQ,
64 CRIME_RE_EMPTY_L_IRQ,
65 CRIME_RE_FULL_L_IRQ,
66 CRIME_RE_IDLE_L_IRQ,
67 CRIME_SOFT0_IRQ,
68 CRIME_SOFT1_IRQ,
69 CRIME_SOFT2_IRQ,
70 CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
71 CRIME_VICE_IRQ,
72
73 /*
74 * MACEISA
75 */
76 MACEISA_AUDIO_SW_IRQ,
77 MACEISA_AUDIO_SC_IRQ,
78 MACEISA_AUDIO1_DMAT_IRQ,
79 MACEISA_AUDIO1_OF_IRQ,
80 MACEISA_AUDIO2_DMAT_IRQ,
81 MACEISA_AUDIO2_MERR_IRQ,
82 MACEISA_AUDIO3_DMAT_IRQ,
83 MACEISA_AUDIO3_MERR_IRQ,
84 MACEISA_RTC_IRQ,
85 MACEISA_KEYB_IRQ,
86 /* MACEISA_KEYB_POLL is not an IRQ */
87 __MACEISA_KEYB_POLL,
88 MACEISA_MOUSE_IRQ,
89 /* MACEISA_MOUSE_POLL is not an IRQ */
90 __MACEISA_MOUSE_POLL,
91 MACEISA_TIMER0_IRQ,
92 MACEISA_TIMER1_IRQ,
93 MACEISA_TIMER2_IRQ,
94 MACEISA_PARALLEL_IRQ,
95 MACEISA_PAR_CTXA_IRQ,
96 MACEISA_PAR_CTXB_IRQ,
97 MACEISA_PAR_MERR_IRQ,
98 MACEISA_SERIAL1_IRQ,
99 MACEISA_SERIAL1_TDMAT_IRQ,
100 MACEISA_SERIAL1_TDMAPR_IRQ,
101 MACEISA_SERIAL1_TDMAME_IRQ,
102 MACEISA_SERIAL1_RDMAT_IRQ,
103 MACEISA_SERIAL1_RDMAOR_IRQ,
104 MACEISA_SERIAL2_IRQ,
105 MACEISA_SERIAL2_TDMAT_IRQ,
106 MACEISA_SERIAL2_TDMAPR_IRQ,
107 MACEISA_SERIAL2_TDMAME_IRQ,
108 MACEISA_SERIAL2_RDMAT_IRQ,
109 MACEISA_SERIAL2_RDMAOR_IRQ,
110
111 IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
112};
113
114#endif /* __ASM_IP32_INTS_H */
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
deleted file mode 100644
index d08d7c672139..000000000000
--- a/include/asm-mips/ip32/mace.h
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2004 Ladislav Michl
10 */
11
12#ifndef __ASM_MACE_H__
13#define __ASM_MACE_H__
14
15/*
16 * Address map
17 */
18#define MACE_BASE 0x1f000000 /* physical */
19
20/*
21 * PCI interface
22 */
23struct mace_pci {
24 volatile unsigned int error_addr;
25 volatile unsigned int error;
26#define MACEPCI_ERROR_MASTER_ABORT BIT(31)
27#define MACEPCI_ERROR_TARGET_ABORT BIT(30)
28#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
29#define MACEPCI_ERROR_RETRY_ERR BIT(28)
30#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
31#define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
32#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
33#define MACEPCI_ERROR_PARITY_ERR BIT(24)
34#define MACEPCI_ERROR_OVERRUN BIT(23)
35#define MACEPCI_ERROR_RSVD BIT(22)
36#define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
37#define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
38#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
39#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
40#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
41#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
42#define MACEPCI_ERROR_SIG_TABORT BIT(4)
43#define MACEPCI_ERROR_DEVSEL_MASK 0xc0
44#define MACEPCI_ERROR_DEVSEL_FAST 0
45#define MACEPCI_ERROR_DEVSEL_MED 0x40
46#define MACEPCI_ERROR_DEVSEL_SLOW 0x80
47#define MACEPCI_ERROR_FBB BIT(1)
48#define MACEPCI_ERROR_66MHZ BIT(0)
49 volatile unsigned int control;
50#define MACEPCI_CONTROL_INT(x) BIT(x)
51#define MACEPCI_CONTROL_INT_MASK 0xff
52#define MACEPCI_CONTROL_SERR_ENA BIT(8)
53#define MACEPCI_CONTROL_ARB_N6 BIT(9)
54#define MACEPCI_CONTROL_PARITY_ERR BIT(10)
55#define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
56#define MACEPCI_CONTROL_ARB_N3 BIT(12)
57#define MACEPCI_CONTROL_ARB_N4 BIT(13)
58#define MACEPCI_CONTROL_ARB_N5 BIT(14)
59#define MACEPCI_CONTROL_PARK_LIU BIT(15)
60#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
61#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
62#define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
63#define MACEPCI_CONTROL_PARITY_INT BIT(25)
64#define MACEPCI_CONTROL_SERR_INT BIT(26)
65#define MACEPCI_CONTROL_IT_INT BIT(27)
66#define MACEPCI_CONTROL_RE_INT BIT(28)
67#define MACEPCI_CONTROL_DPED_INT BIT(29)
68#define MACEPCI_CONTROL_TAR_INT BIT(30)
69#define MACEPCI_CONTROL_MAR_INT BIT(31)
70 volatile unsigned int rev;
71 unsigned int _pad[0xcf8/4 - 4];
72 volatile unsigned int config_addr;
73 union {
74 volatile unsigned char b[4];
75 volatile unsigned short w[2];
76 volatile unsigned int l;
77 } config_data;
78};
79#define MACEPCI_LOW_MEMORY 0x1a000000
80#define MACEPCI_LOW_IO 0x18000000
81#define MACEPCI_SWAPPED_VIEW 0
82#define MACEPCI_NATIVE_VIEW 0x40000000
83#define MACEPCI_IO 0x80000000
84#define MACEPCI_HI_MEMORY 0x280000000
85#define MACEPCI_HI_IO 0x100000000
86
87/*
88 * Video interface
89 */
90struct mace_video {
91 unsigned long xxx; /* later... */
92};
93
94/*
95 * Ethernet interface
96 */
97struct mace_ethernet {
98 volatile unsigned long mac_ctrl;
99 volatile unsigned long int_stat;
100 volatile unsigned long dma_ctrl;
101 volatile unsigned long timer;
102 volatile unsigned long tx_int_al;
103 volatile unsigned long rx_int_al;
104 volatile unsigned long tx_info;
105 volatile unsigned long tx_info_al;
106 volatile unsigned long rx_buff;
107 volatile unsigned long rx_buff_al1;
108 volatile unsigned long rx_buff_al2;
109 volatile unsigned long diag;
110 volatile unsigned long phy_data;
111 volatile unsigned long phy_regs;
112 volatile unsigned long phy_trans_go;
113 volatile unsigned long backoff_seed;
114 /*===================================*/
115 volatile unsigned long imq_reserved[4];
116 volatile unsigned long mac_addr;
117 volatile unsigned long mac_addr2;
118 volatile unsigned long mcast_filter;
119 volatile unsigned long tx_ring_base;
120 /* Following are read-only registers for debugging */
121 volatile unsigned long tx_pkt1_hdr;
122 volatile unsigned long tx_pkt1_ptr[3];
123 volatile unsigned long tx_pkt2_hdr;
124 volatile unsigned long tx_pkt2_ptr[3];
125 /*===================================*/
126 volatile unsigned long rx_fifo;
127};
128
129/*
130 * Peripherals
131 */
132
133/* Audio registers */
134struct mace_audio {
135 volatile unsigned long control;
136 volatile unsigned long codec_control; /* codec status control */
137 volatile unsigned long codec_mask; /* codec status input mask */
138 volatile unsigned long codec_read; /* codec status read data */
139 struct {
140 volatile unsigned long control; /* channel control */
141 volatile unsigned long read_ptr; /* channel read pointer */
142 volatile unsigned long write_ptr; /* channel write pointer */
143 volatile unsigned long depth; /* channel depth */
144 } chan[3];
145};
146
147
148/* register definitions for parallel port DMA */
149struct mace_parport {
150 /* 0 - do nothing,
151 * 1 - pulse terminal count to the device after buffer is drained */
152#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
153 /* Should not cross 4K page boundary */
154#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL
155#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL
156#define MACEPAR_CONTEXT_DATALEN_SHIFT 32
157 /* Can be arbitrarily aligned on any byte boundary on output,
158 * 64 byte aligned on input */
159#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL
160 volatile u64 context_a;
161 volatile u64 context_b;
162 /* 0 - mem->device, 1 - device->mem */
163#define MACEPAR_CTLSTAT_DIRECTION BIT(0)
164 /* 0 - channel frozen, 1 - channel enabled */
165#define MACEPAR_CTLSTAT_ENABLE BIT(1)
166 /* 0 - channel active, 1 - complete channel reset */
167#define MACEPAR_CTLSTAT_RESET BIT(2)
168#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
169#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
170 volatile u64 cntlstat; /* Control/Status register */
171#define MACEPAR_DIAG_CTXINUSE BIT(0)
172 /* 1 - Dma engine is enabled and processing something */
173#define MACEPAR_DIAG_DMACTIVE BIT(1)
174 /* Counter of bytes left */
175#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL
176#define MACEPAR_DIAG_CTRSHIFT 2
177 volatile u64 diagnostic; /* RO: diagnostic register */
178};
179
180/* ISA Control and DMA registers */
181struct mace_isactrl {
182 volatile unsigned long ringbase;
183#define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
184
185 volatile unsigned long misc;
186#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
187#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
188#define MACEISA_NIC_DEASSERT BIT(2)
189#define MACEISA_NIC_DATA BIT(3)
190#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */
191#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */
192#define MACEISA_DP_RAM_ENABLE BIT(6)
193
194 volatile unsigned long istat;
195 volatile unsigned long imask;
196#define MACEISA_AUDIO_SW_INT BIT(0)
197#define MACEISA_AUDIO_SC_INT BIT(1)
198#define MACEISA_AUDIO1_DMAT_INT BIT(2)
199#define MACEISA_AUDIO1_OF_INT BIT(3)
200#define MACEISA_AUDIO2_DMAT_INT BIT(4)
201#define MACEISA_AUDIO2_MERR_INT BIT(5)
202#define MACEISA_AUDIO3_DMAT_INT BIT(6)
203#define MACEISA_AUDIO3_MERR_INT BIT(7)
204#define MACEISA_RTC_INT BIT(8)
205#define MACEISA_KEYB_INT BIT(9)
206#define MACEISA_KEYB_POLL_INT BIT(10)
207#define MACEISA_MOUSE_INT BIT(11)
208#define MACEISA_MOUSE_POLL_INT BIT(12)
209#define MACEISA_TIMER0_INT BIT(13)
210#define MACEISA_TIMER1_INT BIT(14)
211#define MACEISA_TIMER2_INT BIT(15)
212#define MACEISA_PARALLEL_INT BIT(16)
213#define MACEISA_PAR_CTXA_INT BIT(17)
214#define MACEISA_PAR_CTXB_INT BIT(18)
215#define MACEISA_PAR_MERR_INT BIT(19)
216#define MACEISA_SERIAL1_INT BIT(20)
217#define MACEISA_SERIAL1_TDMAT_INT BIT(21)
218#define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
219#define MACEISA_SERIAL1_TDMAME_INT BIT(23)
220#define MACEISA_SERIAL1_RDMAT_INT BIT(24)
221#define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
222#define MACEISA_SERIAL2_INT BIT(26)
223#define MACEISA_SERIAL2_TDMAT_INT BIT(27)
224#define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
225#define MACEISA_SERIAL2_TDMAME_INT BIT(29)
226#define MACEISA_SERIAL2_RDMAT_INT BIT(30)
227#define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
228
229 volatile unsigned long _pad[0x2000/8 - 4];
230
231 volatile unsigned long dp_ram[0x400];
232 struct mace_parport parport;
233};
234
235/* Keyboard & Mouse registers
236 * -> drivers/input/serio/maceps2.c */
237struct mace_ps2port {
238 volatile unsigned long tx;
239 volatile unsigned long rx;
240 volatile unsigned long control;
241 volatile unsigned long status;
242};
243
244struct mace_ps2 {
245 struct mace_ps2port keyb;
246 struct mace_ps2port mouse;
247};
248
249/* I2C registers
250 * -> drivers/i2c/algos/i2c-algo-sgi.c */
251struct mace_i2c {
252 volatile unsigned long config;
253#define MACEI2C_RESET BIT(0)
254#define MACEI2C_FAST BIT(1)
255#define MACEI2C_DATA_OVERRIDE BIT(2)
256#define MACEI2C_CLOCK_OVERRIDE BIT(3)
257#define MACEI2C_DATA_STATUS BIT(4)
258#define MACEI2C_CLOCK_STATUS BIT(5)
259 volatile unsigned long control;
260 volatile unsigned long data;
261};
262
263/* Timer registers */
264typedef union {
265 volatile unsigned long ust_msc;
266 struct reg {
267 volatile unsigned int ust;
268 volatile unsigned int msc;
269 } reg;
270} timer_reg;
271
272struct mace_timers {
273 volatile unsigned long ust;
274#define MACE_UST_PERIOD_NS 960
275
276 volatile unsigned long compare1;
277 volatile unsigned long compare2;
278 volatile unsigned long compare3;
279
280 timer_reg audio_in;
281 timer_reg audio_out1;
282 timer_reg audio_out2;
283 timer_reg video_in1;
284 timer_reg video_in2;
285 timer_reg video_out;
286};
287
288struct mace_perif {
289 struct mace_audio audio;
290 char _pad0[0x10000 - sizeof(struct mace_audio)];
291
292 struct mace_isactrl ctrl;
293 char _pad1[0x10000 - sizeof(struct mace_isactrl)];
294
295 struct mace_ps2 ps2;
296 char _pad2[0x10000 - sizeof(struct mace_ps2)];
297
298 struct mace_i2c i2c;
299 char _pad3[0x10000 - sizeof(struct mace_i2c)];
300
301 struct mace_timers timers;
302 char _pad4[0x10000 - sizeof(struct mace_timers)];
303};
304
305
306/*
307 * ISA peripherals
308 */
309
310/* Parallel port */
311struct mace_parallel {
312};
313
314struct mace_ecp1284 { /* later... */
315};
316
317/* Serial port */
318struct mace_serial {
319 volatile unsigned long xxx; /* later... */
320};
321
322struct mace_isa {
323 struct mace_parallel parallel;
324 char _pad1[0x8000 - sizeof(struct mace_parallel)];
325
326 struct mace_ecp1284 ecp1284;
327 char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
328
329 struct mace_serial serial1;
330 char _pad3[0x8000 - sizeof(struct mace_serial)];
331
332 struct mace_serial serial2;
333 char _pad4[0x8000 - sizeof(struct mace_serial)];
334
335 volatile unsigned char rtc[0x10000];
336};
337
338struct sgi_mace {
339 char _reserved[0x80000];
340
341 struct mace_pci pci;
342 char _pad0[0x80000 - sizeof(struct mace_pci)];
343
344 struct mace_video video_in1;
345 char _pad1[0x80000 - sizeof(struct mace_video)];
346
347 struct mace_video video_in2;
348 char _pad2[0x80000 - sizeof(struct mace_video)];
349
350 struct mace_video video_out;
351 char _pad3[0x80000 - sizeof(struct mace_video)];
352
353 struct mace_ethernet eth;
354 char _pad4[0x80000 - sizeof(struct mace_ethernet)];
355
356 struct mace_perif perif;
357 char _pad5[0x80000 - sizeof(struct mace_perif)];
358
359 struct mace_isa isa;
360 char _pad6[0x80000 - sizeof(struct mace_isa)];
361};
362
363extern struct sgi_mace __iomem *mace;
364
365#endif /* __ASM_MACE_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 22:09:37 -0500