Merge branch 'master'

1 files changed, 47 insertions, 11 deletions

diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index f524eaccd5f1..7517189e469f 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -74,7 +74,8 @@
 #define irq_disable_hazard
         _ehb
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+      defined(CONFIG_CPU_SB1)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -107,6 +108,7 @@ __asm__(
         "       .endm                                           \n\t");
 
 #ifdef CONFIG_CPU_RM9000
+
 /*
  * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
  * use of the JTLB for instructions should not occur for 4 cpu cycles and use
@@ -124,6 +126,9 @@ __asm__(
                 ".set\tmips32\n\t"                                      \
                 "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
                 ".set\tmips0")
+
+#define back_to_back_c0_hazard()        do { } while (0)
+
 #else
 
 /*
@@ -144,15 +149,13 @@ __asm__(
 #endif
 
 /*
- * mtc0->mfc0 hazard
- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
- * It is a MIPS32R2 processor so ehb will clear the hazard.
+ * Interrupt enable/disable hazards
+ * Some processors have hazards when modifying
+ * the status register to change the interrupt state
  */
 
 #ifdef CONFIG_CPU_MIPSR2
-/*
- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
- */
+
 __asm__(
         "       .macro\tirq_enable_hazard                       \n\t"
         "       _ehb                                            \n\t"
@@ -160,17 +163,26 @@ __asm__(
         "                                                       \n\t"
         "       .macro\tirq_disable_hazard                      \n\t"
         "       _ehb                                            \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro\tback_to_back_c0_hazard                  \n\t"
+        "       _ehb                                            \n\t"
         "       .endm");
 
 #define irq_enable_hazard()                                             \
         __asm__ __volatile__(                                           \
-        "_ehb\t\t\t\t# irq_enable_hazard")
+        "irq_enable_hazard")
 
 #define irq_disable_hazard()                                            \
         __asm__ __volatile__(                                           \
-        "_ehb\t\t\t\t# irq_disable_hazard")
+        "irq_disable_hazard")
+
+#define back_to_back_c0_hazard()                                        \
+        __asm__ __volatile__(                                           \
+        "back_to_back_c0_hazard")
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+      defined(CONFIG_CPU_SB1)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -186,6 +198,8 @@ __asm__(
 #define irq_enable_hazard()     do { } while (0)
 #define irq_disable_hazard()    do { } while (0)
 
+#define back_to_back_c0_hazard()        do { } while (0)
+
 #else
 
 /*
@@ -208,10 +222,32 @@ __asm__(
 #define irq_enable_hazard()     do { } while (0)
 #define irq_disable_hazard()                                            \
         __asm__ __volatile__(                                           \
-        "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
+        "irq_disable_hazard")
+
+#define back_to_back_c0_hazard()                                        \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                          \n"             \
+        "       nop; nop; nop                           \n"             \
+        "       .set reorder                            \n")
 
 #endif
 
+#ifdef CONFIG_CPU_MIPSR2
+#define instruction_hazard()                                            \
+do {                                                                    \
+__label__ __next;                                                       \
+        __asm__ __volatile__(                                           \
+        "       jr.hb   %0                                      \n"     \
+        :                                                               \
+        : "r" (&&__next));                                              \
+__next:                                                                 \
+        ;                                                               \
+} while (0)
+
+#else
+#define instruction_hazard() do { } while (0)
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_HAZARDS_H */