From 5068debff2dcbc8f624811e3c06d60c7c0bba744 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 1 Mar 2005 18:12:06 +0000 Subject: New hazard handling function back_to_back_c0_hazard() to handle back to back mtc0 / mfc0 pairs from the same coprocessor register. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include/asm-mips/hazards.h') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index f524eaccd5f1..d6e88cf06ba9 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -124,6 +124,9 @@ __asm__( ".set\tmips32\n\t" \ "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ ".set\tmips0") + +#define back_to_back_c0_hazard() do { } while (0) + #else /* @@ -141,6 +144,12 @@ __asm__( "nop; nop; nop; nop; nop; nop;\n\t" \ ".set reorder\n\t") +#define back_to_back_c0_hazard() \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " nop; nop; nop \n" \ + " .set reorder \n") + #endif /* @@ -170,6 +179,10 @@ __asm__( __asm__ __volatile__( \ "_ehb\t\t\t\t# irq_disable_hazard") +#define back_to_back_c0_hazard() \ + __asm__ __volatile__( \ + "_ehb\t\t\t\t# back_to_back_c0_hazard") + #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) /* @@ -186,6 +199,8 @@ __asm__( #define irq_enable_hazard() do { } while (0) #define irq_disable_hazard() do { } while (0) +#define back_to_back_c0_hazard() do { } while (0) + #else /* @@ -210,6 +225,12 @@ __asm__( __asm__ __volatile__( \ "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") +#define back_to_back_c0_hazard() \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " nop; nop; nop \n" \ + " .set reorder \n") + #endif #endif /* __ASSEMBLY__ */ -- cgit v1.2.2 From 88d535b6b58632bc51ee9a1f35ddfc357e365c37 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 2 Mar 2005 19:18:46 +0000 Subject: One definition of back_to_back_c0_hazard too much. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'include/asm-mips/hazards.h') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index d6e88cf06ba9..181f08de889c 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -107,6 +107,7 @@ __asm__( " .endm \n\t"); #ifdef CONFIG_CPU_RM9000 + /* * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent * use of the JTLB for instructions should not occur for 4 cpu cycles and use @@ -144,12 +145,6 @@ __asm__( "nop; nop; nop; nop; nop; nop;\n\t" \ ".set reorder\n\t") -#define back_to_back_c0_hazard() \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " nop; nop; nop \n" \ - " .set reorder \n") - #endif /* -- cgit v1.2.2 From cc61c1fede7d02cb8133ab0952ca3f3ba1f7fbb1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 12 Jul 2005 18:35:38 +0000 Subject: MIPS R2 instruction hazard handling. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include/asm-mips/hazards.h') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 181f08de889c..f63d824e6e48 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -228,6 +228,22 @@ __asm__( #endif +#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2) +#define instruction_hazard() \ +do { \ +__label__ __next; \ + __asm__ __volatile__( \ + " jr.hb %0 \n" \ + : \ + : "r" (&&__next)); \ +__next: \ + ; \ +} while (0) + +#else +#define instruction_hazard() do { } while (0) +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_HAZARDS_H */ -- cgit v1.2.2 From 86071b637db7baf599df26fdf820dce2fc55ca9f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 14 Jul 2005 13:25:05 +0000 Subject: Cleanups. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'include/asm-mips/hazards.h') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index f63d824e6e48..6bd265b34a4c 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -148,15 +148,13 @@ __asm__( #endif /* - * mtc0->mfc0 hazard - * The 24K has a 2 cycle mtc0/mfc0 execution hazard. - * It is a MIPS32R2 processor so ehb will clear the hazard. + * Interrupt enable/disable hazards + * Some processors have hazards when modifying + * the status register to change the interrupt state */ #ifdef CONFIG_CPU_MIPSR2 -/* - * Use a macro for ehb unless explicit support for MIPSR2 is enabled - */ + __asm__( " .macro\tirq_enable_hazard \n\t" " _ehb \n\t" @@ -164,19 +162,23 @@ __asm__( " \n\t" " .macro\tirq_disable_hazard \n\t" " _ehb \n\t" + " .endm \n\t" + " \n\t" + " .macro\tback_to_back_c0_hazard \n\t" + " _ehb \n\t" " .endm"); #define irq_enable_hazard() \ __asm__ __volatile__( \ - "_ehb\t\t\t\t# irq_enable_hazard") + "irq_enable_hazard") #define irq_disable_hazard() \ __asm__ __volatile__( \ - "_ehb\t\t\t\t# irq_disable_hazard") + "irq_disable_hazard") #define back_to_back_c0_hazard() \ __asm__ __volatile__( \ - "_ehb\t\t\t\t# back_to_back_c0_hazard") + "back_to_back_c0_hazard") #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) @@ -218,7 +220,7 @@ __asm__( #define irq_enable_hazard() do { } while (0) #define irq_disable_hazard() \ __asm__ __volatile__( \ - "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") + "irq_disable_hazard") #define back_to_back_c0_hazard() \ __asm__ __volatile__( \ -- cgit v1.2.2 From f5cfa980e535e1f77038f8037422594592208695 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 1 Oct 2005 11:14:17 +0100 Subject: Use R4000 TLB routines for SB1 also. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include/asm-mips/hazards.h') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 6bd265b34a4c..5250231e936e 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -74,7 +74,8 @@ #define irq_disable_hazard _ehb -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ + defined(CONFIG_CPU_SB1) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. @@ -180,7 +181,8 @@ __asm__( __asm__ __volatile__( \ "back_to_back_c0_hazard") -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ + defined(CONFIG_CPU_SB1) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. -- cgit v1.2.2 From ec917c2c1ab4359a1d438e62daeb50cc42e632e1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 7 Oct 2005 16:58:15 +0100 Subject: Fixup a few lose ends in explicit support for MIPS R1/R2. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-mips/hazards.h') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 5250231e936e..7517189e469f 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -232,7 +232,7 @@ __asm__( #endif -#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2) +#ifdef CONFIG_CPU_MIPSR2 #define instruction_hazard() \ do { \ __label__ __next; \ -- cgit v1.2.2