System-specific handling of bus errors for DECstation variations

supporting parity errors only for memory (Pmax/3min/Maxine).
Fixes for resources decoded by the KN04/KN05 MB ASIC.  Additional
clean-ups for the ECC handler.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

5 files changed, 92 insertions, 51 deletions

diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
index 724908b0bf13..19495a490e72 100644
--- a/include/asm-mips/dec/ecc.h
+++ b/include/asm-mips/dec/ecc.h
@@ -49,7 +49,8 @@ struct pt_regs;
 
 extern void dec_ecc_be_init(void);
 extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id,
+                                        struct pt_regs *regs);
 #endif
 
 #endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
index 325fcbbbdfa0..607a385ffd8a 100644
--- a/include/asm-mips/dec/kn01.h
+++ b/include/asm-mips/dec/kn01.h
@@ -8,7 +8,7 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_DEC_KN01_H
 #define __ASM_MIPS_DEC_KN01_H
@@ -80,4 +80,22 @@
 #define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
 #define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
 
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct pt_regs;
+
+extern u16 cached_kn01_csr;
+extern spinlock_t kn01_lock;
+
+extern void dec_kn01_be_init(void);
+extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
+                                         struct pt_regs *regs);
+#endif
+
 #endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index 2c935f972c67..83a042e90687 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -8,16 +8,11 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_DEC_KN02_H
 #define __ASM_MIPS_DEC_KN02_H
 
-#ifndef __ASSEMBLY__
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#endif
-
 #include <asm/addrspace.h>
 #include <asm/dec/ecc.h>
 
@@ -53,8 +48,8 @@
 #define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
 #define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
 #define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
-#define KN03_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
-#define KN03_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
+#define KN02_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
+#define KN02_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
 #define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
 #define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
 #define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
@@ -63,8 +58,8 @@
 #define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
 #define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
 #define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
-#define KN03_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
-#define KN03_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
+#define KN02_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
+#define KN02_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
 
 
 /*
@@ -98,6 +93,10 @@
 
 
 #ifndef __ASSEMBLY__
+
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
 extern u32 cached_kn02_csr;
 extern spinlock_t kn02_lock;
 extern void init_kn02_irqs(int base);
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
index f6bdf730d9fb..3c25a3346f3f 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/include/asm-mips/dec/kn02xa.h
@@ -9,7 +9,7 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
  *
  * These are addresses which have to be known early in the boot process.
  * For other addresses refer to tc.h, ioasic_addrs.h and friends.
@@ -52,8 +52,13 @@
 #define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
 #define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
 #define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
-#define KN02XA_MER_RES_12       (0x3<<12)       /* unused */
-#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask */
+#define KN02XA_MER_SIZE         (1<<13)         /* r/o mirror of MSR_SIZE */
+#define KN02XA_MER_RES_12       (1<<12)         /* unused */
+#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask: */
+#define KN02XA_MER_BYTERR_3     (0x8<<8)        /* byte lane #3 */
+#define KN02XA_MER_BYTERR_2     (0x4<<8)        /* byte lane #2 */
+#define KN02XA_MER_BYTERR_1     (0x2<<8)        /* byte lane #1 */
+#define KN02XA_MER_BYTERR_0     (0x1<<8)        /* byte lane #0 */
 #define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
 
 /*
@@ -72,4 +77,17 @@
 #define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
 #define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
 
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_kn02xa_be_init(void);
+extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
+                                           struct pt_regs *regs);
+#endif
+
 #endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index b120362b8f13..61feac382efb 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -1,10 +1,12 @@
 /*
  *      include/asm-mips/dec/kn05.h
  *
- *      DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
+ *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
+ *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
+ *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
  *      definitions.
  *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *      Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
@@ -13,59 +15,62 @@
  *
  *      WARNING!  All this information is pure guesswork based on the
  *      ROM.  It is provided here in hope it will give someone some
- *      food for thought.  No documentation for the KN05 module has
- *      been located so far.
+ *      food for thought.  No documentation for the KN05 nor the KN04
+ *      module has been located so far.
  */
 #ifndef __ASM_MIPS_DEC_KN05_H
 #define __ASM_MIPS_DEC_KN05_H
 
+#include <asm/addrspace.h>
 #include <asm/dec/ioasic_addrs.h>
 
 /*
  * The oncard MB (Memory Buffer) ASIC provides an additional address
  * decoder.  Certain address ranges within the "high" 16 slots are
- * passed to the I/O ASIC's decoder like with the KN03.  Others are
- * handled locally.  "Low" slots are always passed.
+ * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
+ * Others are handled locally.  "Low" slots are always passed.
  */
-#define KN05_MB_ROM     (16*IOASIC_SLOT_SIZE)   /* KN05 card ROM */
-#define KN05_IOCTL      (17*IOASIC_SLOT_SIZE)   /* I/O ASIC */
-#define KN05_ESAR       (18*IOASIC_SLOT_SIZE)   /* LANCE MAC address chip */
-#define KN05_LANCE      (19*IOASIC_SLOT_SIZE)   /* LANCE Ethernet */
-#define KN05_MB_INT     (20*IOASIC_SLOT_SIZE)   /* MB interrupt register */
-#define KN05_MB_EA      (21*IOASIC_SLOT_SIZE)   /* MB error address? */
-#define KN05_MB_EC      (22*IOASIC_SLOT_SIZE)   /* MB error ??? */
-#define KN05_MB_CSR     (23*IOASIC_SLOT_SIZE)   /* MB control & status */
-#define KN05_RES_24     (24*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_25     (25*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_26     (26*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_27     (27*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_SCSI       (28*IOASIC_SLOT_SIZE)   /* ASC SCSI */
-#define KN05_RES_29     (29*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_30     (30*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_31     (31*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SLOT_BASE  KSEG1ADDR(0x1fc00000)
+
+#define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
+#define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
+#define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
+#define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
+#define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
+#define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
 
 /*
  * Bits for the MB interrupt register.
  * The register appears read-only.
  */
-#define KN05_MB_INT_TC          (1<<0)          /* TURBOchannel? */
-#define KN05_MB_INT_RTC         (1<<1)          /* RTC? */
-#define KN05_MB_INT_MT          (1<<3)          /* ??? */
+#define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
+#define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
+#define KN4K_MB_INT_MT          (1<<3)          /* ??? */
 
 /*
  * Bits for the MB control & status register.
  * Set to 0x00bf8001 on my system by the ROM.
  */
-#define KN05_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
-#define KN05_MB_CSR_F           (1<<1)          /* ??? */
-#define KN05_MB_CSR_ECC         (0xff<<2)       /* ??? */
-#define KN05_MB_CSR_OD          (1<<10)         /* ??? */
-#define KN05_MB_CSR_CP          (1<<11)         /* ??? */
-#define KN05_MB_CSR_UNC         (1<<12)         /* ??? */
-#define KN05_MB_CSR_IM          (1<<13)         /* ??? */
-#define KN05_MB_CSR_NC          (1<<14)         /* ??? */
-#define KN05_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
-#define KN05_MB_CSR_MSK         (0x1f<<16)      /* ??? */
-#define KN05_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
+#define KN4K_MB_CSR_F           (1<<1)          /* ??? */
+#define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
+#define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
+#define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
+#define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
+#define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
+#define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
+#define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* ??? */
+#define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
 
 #endif /* __ASM_MIPS_DEC_KN05_H */