[MIPS] Define MIPS_CPU_IRQ_BASE in generic header

The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 1 deletions

diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h
index 273e4d65bfe6..e10d341067c8 100644
--- a/include/asm-mips/dec/interrupts.h
+++ b/include/asm-mips/dec/interrupts.h
@@ -14,6 +14,7 @@
 #ifndef __ASM_DEC_INTERRUPTS_H
 #define __ASM_DEC_INTERRUPTS_H
 
+#include <irq.h>
 #include <asm/mipsregs.h>
 
 
@@ -87,7 +88,7 @@
 #define DEC_CPU_INR_SW1         1       /* software #1 */
 #define DEC_CPU_INR_SW0         0       /* software #0 */
 
-#define DEC_CPU_IRQ_BASE        0       /* first IRQ assigned to CPU */
+#define DEC_CPU_IRQ_BASE        MIPS_CPU_IRQ_BASE       /* first IRQ assigned to CPU */
 
 #define DEC_CPU_IRQ_NR(n)       ((n) + DEC_CPU_IRQ_BASE)
 #define DEC_CPU_IRQ_MASK(n)     (1 << ((n) + CAUSEB_IP))