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authorMarc St-Jean <stjeanma@pmc-sierra.com>2007-06-14 17:55:31 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:03 -0400
commit9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa (patch)
tree91fa5a1a4605cdf0a1f1db21e22073b87735ce7a /include/asm-mips/cpu.h
parent35832e26f95ba14a6b6f0519441c5cb64cca6bf9 (diff)
[MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu.h')
-rw-r--r--include/asm-mips/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index a3623954dad1..3857358fb6de 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -109,6 +109,7 @@
109 * Definitions for 7:0 on legacy processors 109 * Definitions for 7:0 on legacy processors
110 */ 110 */
111 111
112#define PRID_REV_MASK 0x00ff
112 113
113#define PRID_REV_TX4927 0x0022 114#define PRID_REV_TX4927 0x0022
114#define PRID_REV_TX4937 0x0030 115#define PRID_REV_TX4937 0x0030
@@ -125,6 +126,7 @@
125#define PRID_REV_VR4122 0x0070 126#define PRID_REV_VR4122 0x0070
126#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 127#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
127#define PRID_REV_VR4130 0x0080 128#define PRID_REV_VR4130 0x0080
129#define PRID_REV_34K_V1_0_2 0x0022
128 130
129/* 131/*
130 * Older processors used to encode processor version and revision in two 132 * Older processors used to encode processor version and revision in two