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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-m68knommu/m527xsim.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-m68knommu/m527xsim.h')
-rw-r--r--include/asm-m68knommu/m527xsim.h58
1 files changed, 58 insertions, 0 deletions
diff --git a/include/asm-m68knommu/m527xsim.h b/include/asm-m68knommu/m527xsim.h
new file mode 100644
index 000000000000..d280d013da03
--- /dev/null
+++ b/include/asm-m68knommu/m527xsim.h
@@ -0,0 +1,58 @@
1/****************************************************************************/
2
3/*
4 * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m527xsim_h
11#define m527xsim_h
12/****************************************************************************/
13
14#include <linux/config.h>
15
16/*
17 * Define the 5270/5271 SIM register set addresses.
18 */
19#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
20#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
21#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
22#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
23#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
24#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
25#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
26#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
27#define MCFINTC_IRLR 0x18 /* */
28#define MCFINTC_IACKL 0x19 /* */
29#define MCFINTC_ICR0 0x40 /* Base ICR register */
30
31#define MCFINT_VECBASE 64 /* Vector base number */
32#define MCFINT_UART0 13 /* Interrupt number for UART0 */
33#define MCFINT_UART1 14 /* Interrupt number for UART1 */
34#define MCFINT_UART2 15 /* Interrupt number for UART2 */
35#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
36
37/*
38 * SDRAM configuration registers.
39 */
40#ifdef CONFIG_M5271EVB
41#define MCFSIM_DCR 0x40 /* SDRAM control */
42#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
43#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
44#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
45#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
46#else
47#define MCFSIM_DMR 0x40 /* SDRAM mode */
48#define MCFSIM_DCR 0x44 /* SDRAM control */
49#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
50#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
51#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
52#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
53#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
54#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
55#endif
56
57/****************************************************************************/
58#endif /* m527xsim_h */