[PATCH] m32r: Support M3A-2170(Mappi-III) platform

This patchset is for supporting a new m32r platform, M3A-2170(Mappi-III) evaluation board. An M32R chip multiprocessor is equipped on the board. http://http://www.linux-m32r.org/eng/platform/platform.html * arch/m32r/Kconfig: Support Mappi-III platform. * arch/m32r/kernel/Makefile: ditto. * arch/m32r/kernel/io_mappi3.c: ditto. * arch/m32r/kernel/setup.c: ditto. * arch/m32r/kernel/setup_mappi3.c: ditto. * include/asm-m32r/m32102.h: ditto. * include/asm-m32r/m32r.h: ditto. * include/asm-m32r/mappi3/mappi3_pld.h: ditto. * include/asm-m32r/ide.h: CF support for Mappi-III. * arch/m32r/kernel/setup_mappi3.c: ditto. * arch/m32r/mappi3/defconfig.smp: A default config file for Mappi-III. * arch/m32r/mappi3/dot.gdbinit: A default .gdbinit file for Mappi-III. * arch/m32r/boot/compressed/m32r_sio.c: Modified for Mappi-III - At boot time, m32r-g00ff bootloader makes MMU off for Mappi-III, on the contrary it makes MMU on for Mappi-II. * arch/m32r/kernel/io_mappi2.c: Update comments. * arch/m32r/kernel/setup_mappi2.c: ditto. Signed-off-by: Mamoru Sakugawa <sakugawa@linux-m32r.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
author: Hirokazu Takata <takata@linux-m32r.org> 2005-06-21 20:16:10 -0400
committer: Linus Torvalds <torvalds@ppc970.osdl.org> 2005-06-21 22:07:30 -0400
commit: 2368086344c3d67b0f4aecac39d620fb9b8795c3 (patch)
tree: aa55003e311abf6049acd23f5ff7f8bfd24eca4c /include/asm-m32r/mappi3
parent: d4c477ca5448f19afaaf6c0cfd655009ea9e614d (diff)
1 files changed, 143 insertions, 0 deletions
diff --git a/include/asm-m32r/mappi3/mappi3_pld.h b/include/asm-m32r/mappi3/mappi3_pld.h
new file mode 100644
index 000000000000..3f1551f7f01f
--- /dev/null
+++ b/include/asm-m32r/mappi3/mappi3_pld.h
@@ -0,0 +1,143 @@
+/*
+ * include/asm/mappi3/mappi3_pld.h
+ *
+ * Definitions for Extended IO Logic on MAPPI3 board.
+ *  based on m32700ut_pld.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ */
+#ifndef _MAPPI3_PLD_H
+#define _MAPPI3_PLD_H
+#ifndef __ASSEMBLY__
+/* FIXME:
+ * Some C functions use non-cache address, so can't define non-cache address.
+ */
+#define PLD_BASE                (0x1c000000 /* + NONCACHE_OFFSET */)
+#define __reg8                  (volatile unsigned char *)
+#define __reg16                 (volatile unsigned short *)
+#define __reg32                 (volatile unsigned int *)
+#else
+#define PLD_BASE                (0x1c000000 + NONCACHE_OFFSET)
+#define __reg8
+#define __reg16
+#define __reg32
+#endif  /* __ASSEMBLY__ */
+/* CFC */
+#define PLD_CFRSTCR             __reg16(PLD_BASE + 0x0000)
+#define PLD_CFSTS               __reg16(PLD_BASE + 0x0002)
+#define PLD_CFIMASK             __reg16(PLD_BASE + 0x0004)
+#define PLD_CFBUFCR             __reg16(PLD_BASE + 0x0006)
+#define PLD_CFCR0               __reg16(PLD_BASE + 0x000a)
+#define PLD_CFCR1               __reg16(PLD_BASE + 0x000c)
+/* MMC */
+#define PLD_MMCCR               __reg16(PLD_BASE + 0x4000)
+#define PLD_MMCMOD              __reg16(PLD_BASE + 0x4002)
+#define PLD_MMCSTS              __reg16(PLD_BASE + 0x4006)
+#define PLD_MMCBAUR             __reg16(PLD_BASE + 0x400a)
+#define PLD_MMCCMDBCUT          __reg16(PLD_BASE + 0x400c)
+#define PLD_MMCCDTBCUT          __reg16(PLD_BASE + 0x400e)
+#define PLD_MMCDET              __reg16(PLD_BASE + 0x4010)
+#define PLD_MMCWP               __reg16(PLD_BASE + 0x4012)
+#define PLD_MMCWDATA            __reg16(PLD_BASE + 0x5000)
+#define PLD_MMCRDATA            __reg16(PLD_BASE + 0x6000)
+#define PLD_MMCCMDDATA          __reg16(PLD_BASE + 0x7000)
+#define PLD_MMCRSPDATA          __reg16(PLD_BASE + 0x7006)
+/* Power Control of MMC and CF */
+#define PLD_CPCR                __reg16(PLD_BASE + 0x14000)
+/*==== ICU ====*/
+#define  M32R_IRQ_PC104        (5)   /* INT4(PC/104) */
+#define  M32R_IRQ_I2C          (28)  /* I2C-BUS     */
+#define  PLD_IRQ_CFIREQ       (6)  /* INT5 CFC Card Interrupt */
+#define  PLD_IRQ_CFC_INSERT   (7)  /* INT6 CFC Card Insert */
+#define  PLD_IRQ_CFC_EJECT    (8)  /* INT7 CFC Card Eject */
+#define  PLD_IRQ_MMCCARD      (43)  /* MMC Card Insert */
+#define  PLD_IRQ_MMCIRQ       (44)  /* MMC Transfer Done */
+#if 0
+/* LED Control
+ *
+ * 1: DIP swich side
+ * 2: Reset switch side
+ */
+#define PLD_IOLEDCR             __reg16(PLD_BASE + 0x14002)
+#define PLD_IOLED_1_ON          0x001
+#define PLD_IOLED_1_OFF         0x000
+#define PLD_IOLED_2_ON          0x002
+#define PLD_IOLED_2_OFF         0x000
+/* DIP Switch
+ *  0: Write-protect of Flash Memory (0:protected, 1:non-protected)
+ *  1: -
+ *  2: -
+ *  3: -
+ */
+#define PLD_IOSWSTS             __reg16(PLD_BASE + 0x14004)
+#define PLD_IOSWSTS_IOSW2       0x0200
+#define PLD_IOSWSTS_IOSW1       0x0100
+#define PLD_IOSWSTS_IOWP0       0x0001
+#endif
+/* CRC */
+#define PLD_CRC7DATA            __reg16(PLD_BASE + 0x18000)
+#define PLD_CRC7INDATA          __reg16(PLD_BASE + 0x18002)
+#define PLD_CRC16DATA           __reg16(PLD_BASE + 0x18004)
+#define PLD_CRC16INDATA         __reg16(PLD_BASE + 0x18006)
+#define PLD_CRC16ADATA          __reg16(PLD_BASE + 0x18008)
+#define PLD_CRC16AINDATA        __reg16(PLD_BASE + 0x1800a)
+#if 0
+/* RTC */
+#define PLD_RTCCR               __reg16(PLD_BASE + 0x1c000)
+#define PLD_RTCBAUR             __reg16(PLD_BASE + 0x1c002)
+#define PLD_RTCWRDATA           __reg16(PLD_BASE + 0x1c004)
+#define PLD_RTCRDDATA           __reg16(PLD_BASE + 0x1c006)
+#define PLD_RTCRSTODT           __reg16(PLD_BASE + 0x1c008)
+/* SIO0 */
+#define PLD_ESIO0CR             __reg16(PLD_BASE + 0x20000)
+#define PLD_ESIO0CR_TXEN        0x0001
+#define PLD_ESIO0CR_RXEN        0x0002
+#define PLD_ESIO0MOD0           __reg16(PLD_BASE + 0x20002)
+#define PLD_ESIO0MOD0_CTSS      0x0040
+#define PLD_ESIO0MOD0_RTSS      0x0080
+#define PLD_ESIO0MOD1           __reg16(PLD_BASE + 0x20004)
+#define PLD_ESIO0MOD1_LMFS      0x0010
+#define PLD_ESIO0STS            __reg16(PLD_BASE + 0x20006)
+#define PLD_ESIO0STS_TEMP       0x0001
+#define PLD_ESIO0STS_TXCP       0x0002
+#define PLD_ESIO0STS_RXCP       0x0004
+#define PLD_ESIO0STS_TXSC       0x0100
+#define PLD_ESIO0STS_RXSC       0x0200
+#define PLD_ESIO0STS_TXREADY    (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
+#define PLD_ESIO0INTCR          __reg16(PLD_BASE + 0x20008)
+#define PLD_ESIO0INTCR_TXIEN    0x0002
+#define PLD_ESIO0INTCR_RXCEN    0x0004
+#define PLD_ESIO0BAUR           __reg16(PLD_BASE + 0x2000a)
+#define PLD_ESIO0TXB            __reg16(PLD_BASE + 0x2000c)
+#define PLD_ESIO0RXB            __reg16(PLD_BASE + 0x2000e)
+/* SIM Card */
+#define PLD_SCCR                __reg16(PLD_BASE + 0x38000)
+#define PLD_SCMOD               __reg16(PLD_BASE + 0x38004)
+#define PLD_SCSTS               __reg16(PLD_BASE + 0x38006)
+#define PLD_SCINTCR             __reg16(PLD_BASE + 0x38008)
+#define PLD_SCBAUR              __reg16(PLD_BASE + 0x3800a)
+#define PLD_SCTXB               __reg16(PLD_BASE + 0x3800c)
+#define PLD_SCRXB               __reg16(PLD_BASE + 0x3800e)
+#endif
+#endif  /* _MAPPI3_PLD.H */
author	Hirokazu Takata <takata@linux-m32r.org>	2005-06-21 20:16:10 -0400
committer	Linus Torvalds <torvalds@ppc970.osdl.org>	2005-06-21 22:07:30 -0400
commit	2368086344c3d67b0f4aecac39d620fb9b8795c3 (patch)
tree	aa55003e311abf6049acd23f5ff7f8bfd24eca4c /include/asm-m32r/mappi3
parent	d4c477ca5448f19afaaf6c0cfd655009ea9e614d (diff)

diff --git a/include/asm-m32r/mappi3/mappi3_pld.h b/include/asm-m32r/mappi3/mappi3_pld.h new file mode 100644 index 000000000000..3f1551f7f01f --- /dev/null +++ b/include/asm-m32r/mappi3/mappi3_pld.h
@@ -0,0 +1,143 @@
	1	/*
	2	* include/asm/mappi3/mappi3_pld.h
	3	*
	4	* Definitions for Extended IO Logic on MAPPI3 board.
	5	* based on m32700ut_pld.h
	6	*
	7	* This file is subject to the terms and conditions of the GNU General
	8	* Public License. See the file "COPYING" in the main directory of
	9	* this archive for more details.
	10	*
	11	*/
	12
	13	#ifndef _MAPPI3_PLD_H
	14	#define _MAPPI3_PLD_H
	15
	16	#ifndef __ASSEMBLY__
	17	/* FIXME:
	18	* Some C functions use non-cache address, so can't define non-cache address.
	19	*/
	20	#define PLD_BASE (0x1c000000 /* + NONCACHE_OFFSET */)
	21	#define __reg8 (volatile unsigned char *)
	22	#define __reg16 (volatile unsigned short *)
	23	#define __reg32 (volatile unsigned int *)
	24	#else
	25	#define PLD_BASE (0x1c000000 + NONCACHE_OFFSET)
	26	#define __reg8
	27	#define __reg16
	28	#define __reg32
	29	#endif /* __ASSEMBLY__ */
	30
	31	/* CFC */
	32	#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
	33	#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
	34	#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
	35	#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
	36	#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
	37	#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
	38
	39	/* MMC */
	40	#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
	41	#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
	42	#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
	43	#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
	44	#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
	45	#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
	46	#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
	47	#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
	48	#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
	49	#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
	50	#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
	51	#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
	52
	53	/* Power Control of MMC and CF */
	54	#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
	55
	56
	57	/==== ICU ====/
	58	#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
	59	#define M32R_IRQ_I2C (28) /* I2C-BUS */
	60	#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */
	61	#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert */
	62	#define PLD_IRQ_CFC_EJECT (8) /* INT7 CFC Card Eject */
	63	#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
	64	#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
	65
	66
	67	#if 0
	68	/* LED Control
	69	*
	70	* 1: DIP swich side
	71	* 2: Reset switch side
	72	*/
	73	#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
	74	#define PLD_IOLED_1_ON 0x001
	75	#define PLD_IOLED_1_OFF 0x000
	76	#define PLD_IOLED_2_ON 0x002
	77	#define PLD_IOLED_2_OFF 0x000
	78
	79	/* DIP Switch
	80	* 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
	81	* 1: -
	82	* 2: -
	83	* 3: -
	84	*/
	85	#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
	86	#define PLD_IOSWSTS_IOSW2 0x0200
	87	#define PLD_IOSWSTS_IOSW1 0x0100
	88	#define PLD_IOSWSTS_IOWP0 0x0001
	89
	90	#endif
	91
	92	/* CRC */
	93	#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
	94	#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
	95	#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
	96	#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
	97	#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
	98	#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
	99
	100
	101	#if 0
	102	/* RTC */
	103	#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
	104	#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
	105	#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
	106	#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
	107	#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
	108
	109	/* SIO0 */
	110	#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
	111	#define PLD_ESIO0CR_TXEN 0x0001
	112	#define PLD_ESIO0CR_RXEN 0x0002
	113	#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
	114	#define PLD_ESIO0MOD0_CTSS 0x0040
	115	#define PLD_ESIO0MOD0_RTSS 0x0080
	116	#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
	117	#define PLD_ESIO0MOD1_LMFS 0x0010
	118	#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
	119	#define PLD_ESIO0STS_TEMP 0x0001
	120	#define PLD_ESIO0STS_TXCP 0x0002
	121	#define PLD_ESIO0STS_RXCP 0x0004
	122	#define PLD_ESIO0STS_TXSC 0x0100
	123	#define PLD_ESIO0STS_RXSC 0x0200
	124	#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP \| PLD_ESIO0STS_TEMP)
	125	#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
	126	#define PLD_ESIO0INTCR_TXIEN 0x0002
	127	#define PLD_ESIO0INTCR_RXCEN 0x0004
	128	#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
	129	#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
	130	#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
	131
	132	/* SIM Card */
	133	#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
	134	#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
	135	#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
	136	#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
	137	#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
	138	#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
	139	#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
	140
	141	#endif
	142
	143	#endif /* _MAPPI3_PLD.H */