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authorTony Luck <tony.luck@intel.com>2008-08-01 13:13:32 -0400
committerTony Luck <tony.luck@intel.com>2008-08-01 13:21:21 -0400
commit7f30491ccd28627742e37899453ae20e3da8e18f (patch)
tree7291c0a26ed3a31acf9542857af3981d278f5de8 /include/asm-ia64/sal.h
parent94ad374a0751f40d25e22e036c37f7263569d24c (diff)
[IA64] Move include/asm-ia64 to arch/ia64/include/asm
After moving the the include files there were a few clean-ups: 1) Some files used #include <asm-ia64/xyz.h>, changed to <asm/xyz.h> 2) Some comments alerted maintainers to look at various header files to make matching updates if certain code were to be changed. Updated these comments to use the new include paths. 3) Some header files mentioned their own names in initial comments. Just deleted these self references. Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/sal.h')
-rw-r--r--include/asm-ia64/sal.h905
1 files changed, 0 insertions, 905 deletions
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
deleted file mode 100644
index 89594b442f83..000000000000
--- a/include/asm-ia64/sal.h
+++ /dev/null
@@ -1,905 +0,0 @@
1#ifndef _ASM_IA64_SAL_H
2#define _ASM_IA64_SAL_H
3
4/*
5 * System Abstraction Layer definitions.
6 *
7 * This is based on version 2.5 of the manual "IA-64 System
8 * Abstraction Layer".
9 *
10 * Copyright (C) 2001 Intel
11 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
13 * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
14 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
18 * revision of the SAL spec.
19 * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
20 * revision of the SAL spec.
21 * 99/09/29 davidm Updated for SAL 2.6.
22 * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
23 * (plus examples of platform error info structures from smariset @ Intel)
24 */
25
26#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT 0
27#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT 1
28#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT 2
29#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT 3
30
31#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT)
32#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT)
33#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT)
34#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT)
35
36#ifndef __ASSEMBLY__
37
38#include <linux/bcd.h>
39#include <linux/spinlock.h>
40#include <linux/efi.h>
41
42#include <asm/pal.h>
43#include <asm/system.h>
44#include <asm/fpu.h>
45
46extern spinlock_t sal_lock;
47
48/* SAL spec _requires_ eight args for each call. */
49#define __IA64_FW_CALL(entry,result,a0,a1,a2,a3,a4,a5,a6,a7) \
50 result = (*entry)(a0,a1,a2,a3,a4,a5,a6,a7)
51
52# define IA64_FW_CALL(entry,result,args...) do { \
53 unsigned long __ia64_sc_flags; \
54 struct ia64_fpreg __ia64_sc_fr[6]; \
55 ia64_save_scratch_fpregs(__ia64_sc_fr); \
56 spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \
57 __IA64_FW_CALL(entry, result, args); \
58 spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \
59 ia64_load_scratch_fpregs(__ia64_sc_fr); \
60} while (0)
61
62# define SAL_CALL(result,args...) \
63 IA64_FW_CALL(ia64_sal, result, args);
64
65# define SAL_CALL_NOLOCK(result,args...) do { \
66 unsigned long __ia64_scn_flags; \
67 struct ia64_fpreg __ia64_scn_fr[6]; \
68 ia64_save_scratch_fpregs(__ia64_scn_fr); \
69 local_irq_save(__ia64_scn_flags); \
70 __IA64_FW_CALL(ia64_sal, result, args); \
71 local_irq_restore(__ia64_scn_flags); \
72 ia64_load_scratch_fpregs(__ia64_scn_fr); \
73} while (0)
74
75# define SAL_CALL_REENTRANT(result,args...) do { \
76 struct ia64_fpreg __ia64_scs_fr[6]; \
77 ia64_save_scratch_fpregs(__ia64_scs_fr); \
78 preempt_disable(); \
79 __IA64_FW_CALL(ia64_sal, result, args); \
80 preempt_enable(); \
81 ia64_load_scratch_fpregs(__ia64_scs_fr); \
82} while (0)
83
84#define SAL_SET_VECTORS 0x01000000
85#define SAL_GET_STATE_INFO 0x01000001
86#define SAL_GET_STATE_INFO_SIZE 0x01000002
87#define SAL_CLEAR_STATE_INFO 0x01000003
88#define SAL_MC_RENDEZ 0x01000004
89#define SAL_MC_SET_PARAMS 0x01000005
90#define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
91
92#define SAL_CACHE_FLUSH 0x01000008
93#define SAL_CACHE_INIT 0x01000009
94#define SAL_PCI_CONFIG_READ 0x01000010
95#define SAL_PCI_CONFIG_WRITE 0x01000011
96#define SAL_FREQ_BASE 0x01000012
97#define SAL_PHYSICAL_ID_INFO 0x01000013
98
99#define SAL_UPDATE_PAL 0x01000020
100
101struct ia64_sal_retval {
102 /*
103 * A zero status value indicates call completed without error.
104 * A negative status value indicates reason of call failure.
105 * A positive status value indicates success but an
106 * informational value should be printed (e.g., "reboot for
107 * change to take effect").
108 */
109 s64 status;
110 u64 v0;
111 u64 v1;
112 u64 v2;
113};
114
115typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
116
117enum {
118 SAL_FREQ_BASE_PLATFORM = 0,
119 SAL_FREQ_BASE_INTERVAL_TIMER = 1,
120 SAL_FREQ_BASE_REALTIME_CLOCK = 2
121};
122
123/*
124 * The SAL system table is followed by a variable number of variable
125 * length descriptors. The structure of these descriptors follows
126 * below.
127 * The defininition follows SAL specs from July 2000
128 */
129struct ia64_sal_systab {
130 u8 signature[4]; /* should be "SST_" */
131 u32 size; /* size of this table in bytes */
132 u8 sal_rev_minor;
133 u8 sal_rev_major;
134 u16 entry_count; /* # of entries in variable portion */
135 u8 checksum;
136 u8 reserved1[7];
137 u8 sal_a_rev_minor;
138 u8 sal_a_rev_major;
139 u8 sal_b_rev_minor;
140 u8 sal_b_rev_major;
141 /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
142 u8 oem_id[32];
143 u8 product_id[32]; /* ASCII product id */
144 u8 reserved2[8];
145};
146
147enum sal_systab_entry_type {
148 SAL_DESC_ENTRY_POINT = 0,
149 SAL_DESC_MEMORY = 1,
150 SAL_DESC_PLATFORM_FEATURE = 2,
151 SAL_DESC_TR = 3,
152 SAL_DESC_PTC = 4,
153 SAL_DESC_AP_WAKEUP = 5
154};
155
156/*
157 * Entry type: Size:
158 * 0 48
159 * 1 32
160 * 2 16
161 * 3 32
162 * 4 16
163 * 5 16
164 */
165#define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
166
167typedef struct ia64_sal_desc_entry_point {
168 u8 type;
169 u8 reserved1[7];
170 u64 pal_proc;
171 u64 sal_proc;
172 u64 gp;
173 u8 reserved2[16];
174}ia64_sal_desc_entry_point_t;
175
176typedef struct ia64_sal_desc_memory {
177 u8 type;
178 u8 used_by_sal; /* needs to be mapped for SAL? */
179 u8 mem_attr; /* current memory attribute setting */
180 u8 access_rights; /* access rights set up by SAL */
181 u8 mem_attr_mask; /* mask of supported memory attributes */
182 u8 reserved1;
183 u8 mem_type; /* memory type */
184 u8 mem_usage; /* memory usage */
185 u64 addr; /* physical address of memory */
186 u32 length; /* length (multiple of 4KB pages) */
187 u32 reserved2;
188 u8 oem_reserved[8];
189} ia64_sal_desc_memory_t;
190
191typedef struct ia64_sal_desc_platform_feature {
192 u8 type;
193 u8 feature_mask;
194 u8 reserved1[14];
195} ia64_sal_desc_platform_feature_t;
196
197typedef struct ia64_sal_desc_tr {
198 u8 type;
199 u8 tr_type; /* 0 == instruction, 1 == data */
200 u8 regnum; /* translation register number */
201 u8 reserved1[5];
202 u64 addr; /* virtual address of area covered */
203 u64 page_size; /* encoded page size */
204 u8 reserved2[8];
205} ia64_sal_desc_tr_t;
206
207typedef struct ia64_sal_desc_ptc {
208 u8 type;
209 u8 reserved1[3];
210 u32 num_domains; /* # of coherence domains */
211 u64 domain_info; /* physical address of domain info table */
212} ia64_sal_desc_ptc_t;
213
214typedef struct ia64_sal_ptc_domain_info {
215 u64 proc_count; /* number of processors in domain */
216 u64 proc_list; /* physical address of LID array */
217} ia64_sal_ptc_domain_info_t;
218
219typedef struct ia64_sal_ptc_domain_proc_entry {
220 u64 id : 8; /* id of processor */
221 u64 eid : 8; /* eid of processor */
222} ia64_sal_ptc_domain_proc_entry_t;
223
224
225#define IA64_SAL_AP_EXTERNAL_INT 0
226
227typedef struct ia64_sal_desc_ap_wakeup {
228 u8 type;
229 u8 mechanism; /* 0 == external interrupt */
230 u8 reserved1[6];
231 u64 vector; /* interrupt vector in range 0x10-0xff */
232} ia64_sal_desc_ap_wakeup_t ;
233
234extern ia64_sal_handler ia64_sal;
235extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
236
237extern unsigned short sal_revision; /* supported SAL spec revision */
238extern unsigned short sal_version; /* SAL version; OEM dependent */
239#define SAL_VERSION_CODE(major, minor) ((BIN2BCD(major) << 8) | BIN2BCD(minor))
240
241extern const char *ia64_sal_strerror (long status);
242extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
243
244/* SAL information type encodings */
245enum {
246 SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
247 SAL_INFO_TYPE_INIT = 1, /* Init information */
248 SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */
249 SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */
250};
251
252/* Encodings for machine check parameter types */
253enum {
254 SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */
255 SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
256 SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */
257};
258
259/* Encodings for rendezvous mechanisms */
260enum {
261 SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
262 SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
263};
264
265/* Encodings for vectors which can be registered by the OS with SAL */
266enum {
267 SAL_VECTOR_OS_MCA = 0,
268 SAL_VECTOR_OS_INIT = 1,
269 SAL_VECTOR_OS_BOOT_RENDEZ = 2
270};
271
272/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
273#define SAL_MC_PARAM_RZ_ALWAYS 0x1
274#define SAL_MC_PARAM_BINIT_ESCALATE 0x10
275
276/*
277 * Definition of the SAL Error Log from the SAL spec
278 */
279
280/* SAL Error Record Section GUID Definitions */
281#define SAL_PROC_DEV_ERR_SECT_GUID \
282 EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
283#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
284 EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
285#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
286 EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
287#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
288 EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
289#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
290 EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
291#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
292 EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
293#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
294 EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
295#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
296 EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
297#define SAL_PLAT_BUS_ERR_SECT_GUID \
298 EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
299#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
300 EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
301 0xca, 0x4d)
302
303#define MAX_CACHE_ERRORS 6
304#define MAX_TLB_ERRORS 6
305#define MAX_BUS_ERRORS 1
306
307/* Definition of version according to SAL spec for logging purposes */
308typedef struct sal_log_revision {
309 u8 minor; /* BCD (0..99) */
310 u8 major; /* BCD (0..99) */
311} sal_log_revision_t;
312
313/* Definition of timestamp according to SAL spec for logging purposes */
314typedef struct sal_log_timestamp {
315 u8 slh_second; /* Second (0..59) */
316 u8 slh_minute; /* Minute (0..59) */
317 u8 slh_hour; /* Hour (0..23) */
318 u8 slh_reserved;
319 u8 slh_day; /* Day (1..31) */
320 u8 slh_month; /* Month (1..12) */
321 u8 slh_year; /* Year (00..99) */
322 u8 slh_century; /* Century (19, 20, 21, ...) */
323} sal_log_timestamp_t;
324
325/* Definition of log record header structures */
326typedef struct sal_log_record_header {
327 u64 id; /* Unique monotonically increasing ID */
328 sal_log_revision_t revision; /* Major and Minor revision of header */
329 u8 severity; /* Error Severity */
330 u8 validation_bits; /* 0: platform_guid, 1: !timestamp */
331 u32 len; /* Length of this error log in bytes */
332 sal_log_timestamp_t timestamp; /* Timestamp */
333 efi_guid_t platform_guid; /* Unique OEM Platform ID */
334} sal_log_record_header_t;
335
336#define sal_log_severity_recoverable 0
337#define sal_log_severity_fatal 1
338#define sal_log_severity_corrected 2
339
340/* Definition of log section header structures */
341typedef struct sal_log_sec_header {
342 efi_guid_t guid; /* Unique Section ID */
343 sal_log_revision_t revision; /* Major and Minor revision of Section */
344 u16 reserved;
345 u32 len; /* Section length */
346} sal_log_section_hdr_t;
347
348typedef struct sal_log_mod_error_info {
349 struct {
350 u64 check_info : 1,
351 requestor_identifier : 1,
352 responder_identifier : 1,
353 target_identifier : 1,
354 precise_ip : 1,
355 reserved : 59;
356 } valid;
357 u64 check_info;
358 u64 requestor_identifier;
359 u64 responder_identifier;
360 u64 target_identifier;
361 u64 precise_ip;
362} sal_log_mod_error_info_t;
363
364typedef struct sal_processor_static_info {
365 struct {
366 u64 minstate : 1,
367 br : 1,
368 cr : 1,
369 ar : 1,
370 rr : 1,
371 fr : 1,
372 reserved : 58;
373 } valid;
374 pal_min_state_area_t min_state_area;
375 u64 br[8];
376 u64 cr[128];
377 u64 ar[128];
378 u64 rr[8];
379 struct ia64_fpreg __attribute__ ((packed)) fr[128];
380} sal_processor_static_info_t;
381
382struct sal_cpuid_info {
383 u64 regs[5];
384 u64 reserved;
385};
386
387typedef struct sal_log_processor_info {
388 sal_log_section_hdr_t header;
389 struct {
390 u64 proc_error_map : 1,
391 proc_state_param : 1,
392 proc_cr_lid : 1,
393 psi_static_struct : 1,
394 num_cache_check : 4,
395 num_tlb_check : 4,
396 num_bus_check : 4,
397 num_reg_file_check : 4,
398 num_ms_check : 4,
399 cpuid_info : 1,
400 reserved1 : 39;
401 } valid;
402 u64 proc_error_map;
403 u64 proc_state_parameter;
404 u64 proc_cr_lid;
405 /*
406 * The rest of this structure consists of variable-length arrays, which can't be
407 * expressed in C.
408 */
409 sal_log_mod_error_info_t info[0];
410 /*
411 * This is what the rest looked like if C supported variable-length arrays:
412 *
413 * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
414 * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
415 * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
416 * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
417 * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
418 * struct sal_cpuid_info cpuid_info;
419 * sal_processor_static_info_t processor_static_info;
420 */
421} sal_log_processor_info_t;
422
423/* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
424#define SAL_LPI_PSI_INFO(l) \
425({ sal_log_processor_info_t *_l = (l); \
426 ((sal_processor_static_info_t *) \
427 ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \
428 + _l->valid.num_bus_check + _l->valid.num_reg_file_check \
429 + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \
430 + sizeof(struct sal_cpuid_info)))); \
431})
432
433/* platform error log structures */
434
435typedef struct sal_log_mem_dev_err_info {
436 sal_log_section_hdr_t header;
437 struct {
438 u64 error_status : 1,
439 physical_addr : 1,
440 addr_mask : 1,
441 node : 1,
442 card : 1,
443 module : 1,
444 bank : 1,
445 device : 1,
446 row : 1,
447 column : 1,
448 bit_position : 1,
449 requestor_id : 1,
450 responder_id : 1,
451 target_id : 1,
452 bus_spec_data : 1,
453 oem_id : 1,
454 oem_data : 1,
455 reserved : 47;
456 } valid;
457 u64 error_status;
458 u64 physical_addr;
459 u64 addr_mask;
460 u16 node;
461 u16 card;
462 u16 module;
463 u16 bank;
464 u16 device;
465 u16 row;
466 u16 column;
467 u16 bit_position;
468 u64 requestor_id;
469 u64 responder_id;
470 u64 target_id;
471 u64 bus_spec_data;
472 u8 oem_id[16];
473 u8 oem_data[1]; /* Variable length data */
474} sal_log_mem_dev_err_info_t;
475
476typedef struct sal_log_sel_dev_err_info {
477 sal_log_section_hdr_t header;
478 struct {
479 u64 record_id : 1,
480 record_type : 1,
481 generator_id : 1,
482 evm_rev : 1,
483 sensor_type : 1,
484 sensor_num : 1,
485 event_dir : 1,
486 event_data1 : 1,
487 event_data2 : 1,
488 event_data3 : 1,
489 reserved : 54;
490 } valid;
491 u16 record_id;
492 u8 record_type;
493 u8 timestamp[4];
494 u16 generator_id;
495 u8 evm_rev;
496 u8 sensor_type;
497 u8 sensor_num;
498 u8 event_dir;
499 u8 event_data1;
500 u8 event_data2;
501 u8 event_data3;
502} sal_log_sel_dev_err_info_t;
503
504typedef struct sal_log_pci_bus_err_info {
505 sal_log_section_hdr_t header;
506 struct {
507 u64 err_status : 1,
508 err_type : 1,
509 bus_id : 1,
510 bus_address : 1,
511 bus_data : 1,
512 bus_cmd : 1,
513 requestor_id : 1,
514 responder_id : 1,
515 target_id : 1,
516 oem_data : 1,
517 reserved : 54;
518 } valid;
519 u64 err_status;
520 u16 err_type;
521 u16 bus_id;
522 u32 reserved;
523 u64 bus_address;
524 u64 bus_data;
525 u64 bus_cmd;
526 u64 requestor_id;
527 u64 responder_id;
528 u64 target_id;
529 u8 oem_data[1]; /* Variable length data */
530} sal_log_pci_bus_err_info_t;
531
532typedef struct sal_log_smbios_dev_err_info {
533 sal_log_section_hdr_t header;
534 struct {
535 u64 event_type : 1,
536 length : 1,
537 time_stamp : 1,
538 data : 1,
539 reserved1 : 60;
540 } valid;
541 u8 event_type;
542 u8 length;
543 u8 time_stamp[6];
544 u8 data[1]; /* data of variable length, length == slsmb_length */
545} sal_log_smbios_dev_err_info_t;
546
547typedef struct sal_log_pci_comp_err_info {
548 sal_log_section_hdr_t header;
549 struct {
550 u64 err_status : 1,
551 comp_info : 1,
552 num_mem_regs : 1,
553 num_io_regs : 1,
554 reg_data_pairs : 1,
555 oem_data : 1,
556 reserved : 58;
557 } valid;
558 u64 err_status;
559 struct {
560 u16 vendor_id;
561 u16 device_id;
562 u8 class_code[3];
563 u8 func_num;
564 u8 dev_num;
565 u8 bus_num;
566 u8 seg_num;
567 u8 reserved[5];
568 } comp_info;
569 u32 num_mem_regs;
570 u32 num_io_regs;
571 u64 reg_data_pairs[1];
572 /*
573 * array of address/data register pairs is num_mem_regs + num_io_regs elements
574 * long. Each array element consists of a u64 address followed by a u64 data
575 * value. The oem_data array immediately follows the reg_data_pairs array
576 */
577 u8 oem_data[1]; /* Variable length data */
578} sal_log_pci_comp_err_info_t;
579
580typedef struct sal_log_plat_specific_err_info {
581 sal_log_section_hdr_t header;
582 struct {
583 u64 err_status : 1,
584 guid : 1,
585 oem_data : 1,
586 reserved : 61;
587 } valid;
588 u64 err_status;
589 efi_guid_t guid;
590 u8 oem_data[1]; /* platform specific variable length data */
591} sal_log_plat_specific_err_info_t;
592
593typedef struct sal_log_host_ctlr_err_info {
594 sal_log_section_hdr_t header;
595 struct {
596 u64 err_status : 1,
597 requestor_id : 1,
598 responder_id : 1,
599 target_id : 1,
600 bus_spec_data : 1,
601 oem_data : 1,
602 reserved : 58;
603 } valid;
604 u64 err_status;
605 u64 requestor_id;
606 u64 responder_id;
607 u64 target_id;
608 u64 bus_spec_data;
609 u8 oem_data[1]; /* Variable length OEM data */
610} sal_log_host_ctlr_err_info_t;
611
612typedef struct sal_log_plat_bus_err_info {
613 sal_log_section_hdr_t header;
614 struct {
615 u64 err_status : 1,
616 requestor_id : 1,
617 responder_id : 1,
618 target_id : 1,
619 bus_spec_data : 1,
620 oem_data : 1,
621 reserved : 58;
622 } valid;
623 u64 err_status;
624 u64 requestor_id;
625 u64 responder_id;
626 u64 target_id;
627 u64 bus_spec_data;
628 u8 oem_data[1]; /* Variable length OEM data */
629} sal_log_plat_bus_err_info_t;
630
631/* Overall platform error section structure */
632typedef union sal_log_platform_err_info {
633 sal_log_mem_dev_err_info_t mem_dev_err;
634 sal_log_sel_dev_err_info_t sel_dev_err;
635 sal_log_pci_bus_err_info_t pci_bus_err;
636 sal_log_smbios_dev_err_info_t smbios_dev_err;
637 sal_log_pci_comp_err_info_t pci_comp_err;
638 sal_log_plat_specific_err_info_t plat_specific_err;
639 sal_log_host_ctlr_err_info_t host_ctlr_err;
640 sal_log_plat_bus_err_info_t plat_bus_err;
641} sal_log_platform_err_info_t;
642
643/* SAL log over-all, multi-section error record structure (processor+platform) */
644typedef struct err_rec {
645 sal_log_record_header_t sal_elog_header;
646 sal_log_processor_info_t proc_err;
647 sal_log_platform_err_info_t plat_err;
648 u8 oem_data_pad[1024];
649} ia64_err_rec_t;
650
651/*
652 * Now define a couple of inline functions for improved type checking
653 * and convenience.
654 */
655
656extern s64 ia64_sal_cache_flush (u64 cache_type);
657extern void __init check_sal_cache_flush (void);
658
659/* Initialize all the processor and platform level instruction and data caches */
660static inline s64
661ia64_sal_cache_init (void)
662{
663 struct ia64_sal_retval isrv;
664 SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
665 return isrv.status;
666}
667
668/*
669 * Clear the processor and platform information logged by SAL with respect to the machine
670 * state at the time of MCA's, INITs, CMCs, or CPEs.
671 */
672static inline s64
673ia64_sal_clear_state_info (u64 sal_info_type)
674{
675 struct ia64_sal_retval isrv;
676 SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
677 0, 0, 0, 0, 0);
678 return isrv.status;
679}
680
681
682/* Get the processor and platform information logged by SAL with respect to the machine
683 * state at the time of the MCAs, INITs, CMCs, or CPEs.
684 */
685static inline u64
686ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
687{
688 struct ia64_sal_retval isrv;
689 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
690 sal_info, 0, 0, 0, 0);
691 if (isrv.status)
692 return 0;
693
694 return isrv.v0;
695}
696
697/*
698 * Get the maximum size of the information logged by SAL with respect to the machine state
699 * at the time of MCAs, INITs, CMCs, or CPEs.
700 */
701static inline u64
702ia64_sal_get_state_info_size (u64 sal_info_type)
703{
704 struct ia64_sal_retval isrv;
705 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
706 0, 0, 0, 0, 0);
707 if (isrv.status)
708 return 0;
709 return isrv.v0;
710}
711
712/*
713 * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
714 * the monarch processor. Must not lock, because it will not return on any cpu until the
715 * monarch processor sends a wake up.
716 */
717static inline s64
718ia64_sal_mc_rendez (void)
719{
720 struct ia64_sal_retval isrv;
721 SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
722 return isrv.status;
723}
724
725/*
726 * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
727 * the machine check rendezvous sequence as well as the mechanism to wake up the
728 * non-monarch processor at the end of machine check processing.
729 * Returns the complete ia64_sal_retval because some calls return more than just a status
730 * value.
731 */
732static inline struct ia64_sal_retval
733ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
734{
735 struct ia64_sal_retval isrv;
736 SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
737 timeout, rz_always, 0, 0);
738 return isrv;
739}
740
741/* Read from PCI configuration space */
742static inline s64
743ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)
744{
745 struct ia64_sal_retval isrv;
746 SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0);
747 if (value)
748 *value = isrv.v0;
749 return isrv.status;
750}
751
752/* Write to PCI configuration space */
753static inline s64
754ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)
755{
756 struct ia64_sal_retval isrv;
757 SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
758 type, 0, 0, 0);
759 return isrv.status;
760}
761
762/*
763 * Register physical addresses of locations needed by SAL when SAL procedures are invoked
764 * in virtual mode.
765 */
766static inline s64
767ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
768{
769 struct ia64_sal_retval isrv;
770 SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
771 0, 0, 0, 0, 0);
772 return isrv.status;
773}
774
775/*
776 * Register software dependent code locations within SAL. These locations are handlers or
777 * entry points where SAL will pass control for the specified event. These event handlers
778 * are for the bott rendezvous, MCAs and INIT scenarios.
779 */
780static inline s64
781ia64_sal_set_vectors (u64 vector_type,
782 u64 handler_addr1, u64 gp1, u64 handler_len1,
783 u64 handler_addr2, u64 gp2, u64 handler_len2)
784{
785 struct ia64_sal_retval isrv;
786 SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
787 handler_addr1, gp1, handler_len1,
788 handler_addr2, gp2, handler_len2);
789
790 return isrv.status;
791}
792
793/* Update the contents of PAL block in the non-volatile storage device */
794static inline s64
795ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
796 u64 *error_code, u64 *scratch_buf_size_needed)
797{
798 struct ia64_sal_retval isrv;
799 SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
800 0, 0, 0, 0);
801 if (error_code)
802 *error_code = isrv.v0;
803 if (scratch_buf_size_needed)
804 *scratch_buf_size_needed = isrv.v1;
805 return isrv.status;
806}
807
808/* Get physical processor die mapping in the platform. */
809static inline s64
810ia64_sal_physical_id_info(u16 *splid)
811{
812 struct ia64_sal_retval isrv;
813
814 if (sal_revision < SAL_VERSION_CODE(3,2))
815 return -1;
816
817 SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
818 if (splid)
819 *splid = isrv.v0;
820 return isrv.status;
821}
822
823extern unsigned long sal_platform_features;
824
825extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
826
827struct sal_ret_values {
828 long r8; long r9; long r10; long r11;
829};
830
831#define IA64_SAL_OEMFUNC_MIN 0x02000000
832#define IA64_SAL_OEMFUNC_MAX 0x03ffffff
833
834extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
835 u64, u64, u64);
836extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
837 u64, u64, u64, u64, u64);
838extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
839 u64, u64, u64, u64, u64);
840extern long
841ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
842 unsigned long *drift_info);
843#ifdef CONFIG_HOTPLUG_CPU
844/*
845 * System Abstraction Layer Specification
846 * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
847 * Note: region regs are stored first in head.S _start. Hence they must
848 * stay up front.
849 */
850struct sal_to_os_boot {
851 u64 rr[8]; /* Region Registers */
852 u64 br[6]; /* br0:
853 * return addr into SAL boot rendez routine */
854 u64 gr1; /* SAL:GP */
855 u64 gr12; /* SAL:SP */
856 u64 gr13; /* SAL: Task Pointer */
857 u64 fpsr;
858 u64 pfs;
859 u64 rnat;
860 u64 unat;
861 u64 bspstore;
862 u64 dcr; /* Default Control Register */
863 u64 iva;
864 u64 pta;
865 u64 itv;
866 u64 pmv;
867 u64 cmcv;
868 u64 lrr[2];
869 u64 gr[4];
870 u64 pr; /* Predicate registers */
871 u64 lc; /* Loop Count */
872 struct ia64_fpreg fp[20];
873};
874
875/*
876 * Global array allocated for NR_CPUS at boot time
877 */
878extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
879
880extern void ia64_jump_to_sal(struct sal_to_os_boot *);
881#endif
882
883extern void ia64_sal_handler_init(void *entry_point, void *gpval);
884
885#define PALO_MAX_TLB_PURGES 0xFFFF
886#define PALO_SIG "PALO"
887
888struct palo_table {
889 u8 signature[4]; /* Should be "PALO" */
890 u32 length;
891 u8 minor_revision;
892 u8 major_revision;
893 u8 checksum;
894 u8 reserved1[5];
895 u16 max_tlb_purges;
896 u8 reserved2[6];
897};
898
899#define NPTCG_FROM_PAL 0
900#define NPTCG_FROM_PALO 1
901#define NPTCG_FROM_KERNEL_PARAMETER 2
902
903#endif /* __ASSEMBLY__ */
904
905#endif /* _ASM_IA64_SAL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 20:18:50 -0500