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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-26 17:17:50 -0500 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-26 17:17:50 -0500 |
commit | 6f8c480f998a619082f18407f8d7f4c29e94dc6e (patch) | |
tree | 5047fe0d685fe9eab64c506fa1001e7df5e65faa /include/asm-i386 | |
parent | 038c068f63a950c3a6ccfa814831ccac0ad48fb1 (diff) | |
parent | bd5ab26a7d0cc834d846fe5dd7291f0aed3be72b (diff) |
Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq
* master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq:
[CPUFREQ] constify some data tables.
[CPUFREQ] constify cpufreq_driver where possible.
{rd,wr}msr_on_cpu SMP=n optimization
[CPUFREQ] cpufreq_ondemand.c: don't use _WORK_NAR
rdmsr_on_cpu, wrmsr_on_cpu
[CPUFREQ] Revert default on deprecated config X86_SPEEDSTEP_CENTRINO_ACPI
Diffstat (limited to 'include/asm-i386')
-rw-r--r-- | include/asm-i386/msr.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index 6db40d0583f1..ec3b6803fd36 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h | |||
@@ -83,6 +83,20 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) | |||
83 | : "c" (counter)) | 83 | : "c" (counter)) |
84 | #endif /* !CONFIG_PARAVIRT */ | 84 | #endif /* !CONFIG_PARAVIRT */ |
85 | 85 | ||
86 | #ifdef CONFIG_SMP | ||
87 | void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); | ||
88 | void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | ||
89 | #else /* CONFIG_SMP */ | ||
90 | static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) | ||
91 | { | ||
92 | rdmsr(msr_no, *l, *h); | ||
93 | } | ||
94 | static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | ||
95 | { | ||
96 | wrmsr(msr_no, l, h); | ||
97 | } | ||
98 | #endif /* CONFIG_SMP */ | ||
99 | |||
86 | /* symbolic names for some interesting MSRs */ | 100 | /* symbolic names for some interesting MSRs */ |
87 | /* Intel defined MSRs. */ | 101 | /* Intel defined MSRs. */ |
88 | #define MSR_IA32_P5_MC_ADDR 0 | 102 | #define MSR_IA32_P5_MC_ADDR 0 |