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authorWill Deacon <will.deacon@arm.com>2013-09-03 05:44:00 -0400
committerWill Deacon <will.deacon@arm.com>2014-10-20 13:49:17 -0400
commit9439eb3ab9d1ece6e4ad7baaa4a7f534f9b9dab0 (patch)
treee0c055ab3595d0f6f865f6aa2bbb0c6d51442adb /include/asm-generic
parentf114040e3ea6e07372334ade75d1ee0775c355e1 (diff)
asm-generic: io: implement relaxed accessor macros as conditional wrappers
{read,write}{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds wrappers to asm-generic so that drivers can rely on the relaxed accessors being available, even if they don't always provide weaker ordering guarantees. Since some architectures both include asm-generic/io.h and define some relaxed accessors, the definitions here are conditional for the time being. Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'include/asm-generic')
-rw-r--r--include/asm-generic/io.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b8fdc57a7335..fc8dc0eb203c 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -53,18 +53,27 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
53#endif 53#endif
54 54
55#define readb __raw_readb 55#define readb __raw_readb
56#ifndef readb_relaxed
57#define readb_relaxed readb
58#endif
56 59
57#define readw readw 60#define readw readw
58static inline u16 readw(const volatile void __iomem *addr) 61static inline u16 readw(const volatile void __iomem *addr)
59{ 62{
60 return __le16_to_cpu(__raw_readw(addr)); 63 return __le16_to_cpu(__raw_readw(addr));
61} 64}
65#ifndef readw_relaxed
66#define readw_relaxed readw
67#endif
62 68
63#define readl readl 69#define readl readl
64static inline u32 readl(const volatile void __iomem *addr) 70static inline u32 readl(const volatile void __iomem *addr)
65{ 71{
66 return __le32_to_cpu(__raw_readl(addr)); 72 return __le32_to_cpu(__raw_readl(addr));
67} 73}
74#ifndef readl_relaxed
75#define readl_relaxed readl
76#endif
68 77
69#ifndef __raw_writeb 78#ifndef __raw_writeb
70static inline void __raw_writeb(u8 b, volatile void __iomem *addr) 79static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
@@ -88,8 +97,19 @@ static inline void __raw_writel(u32 b, volatile void __iomem *addr)
88#endif 97#endif
89 98
90#define writeb __raw_writeb 99#define writeb __raw_writeb
100#ifndef writeb_relaxed
101#define writeb_relaxed writeb
102#endif
103
91#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr) 104#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
105#ifndef writew_relaxed
106#define writew_relaxed writew
107#endif
108
92#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr) 109#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
110#ifndef writel_relaxed
111#define writel_relaxed writel
112#endif
93 113
94#ifdef CONFIG_64BIT 114#ifdef CONFIG_64BIT
95#ifndef __raw_readq 115#ifndef __raw_readq
@@ -104,6 +124,9 @@ static inline u64 readq(const volatile void __iomem *addr)
104{ 124{
105 return __le64_to_cpu(__raw_readq(addr)); 125 return __le64_to_cpu(__raw_readq(addr));
106} 126}
127#ifndef readq_relaxed
128#define readq_relaxed readq
129#endif
107 130
108#ifndef __raw_writeq 131#ifndef __raw_writeq
109static inline void __raw_writeq(u64 b, volatile void __iomem *addr) 132static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
@@ -113,6 +136,9 @@ static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
113#endif 136#endif
114 137
115#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr) 138#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
139#ifndef writeq_relaxed
140#define writeq_relaxed writeq
141#endif
116#endif /* CONFIG_64BIT */ 142#endif /* CONFIG_64BIT */
117 143
118#ifndef PCI_IOBASE 144#ifndef PCI_IOBASE