diff options
author | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-01-28 11:56:56 -0500 |
---|---|---|
committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-02-08 05:06:38 -0500 |
commit | 6c6dc56c1e980dd3b63c9e7b5209167f9afcafcc (patch) | |
tree | 3bcf182a1789334585459e8700a929e2c170f217 /include/asm-cris | |
parent | 8d073287442fd8f56baadd4a17853931b8330e47 (diff) |
CRIS v32: Add support for ETRAX FS and ARTPEC-3 for arch-v32/hwregs/eth_defs.h
- A couple of fields have changed name:
reg_eth_rw_ga_lo.table -> tbl
reg_eth_rw_ga_hi.table -> tbl
reg_eth_rw_gen_ctrl.flow_ctrl_dis -> flow_ctrl
- Add some new register fields.
reg_eth_rw_gen_ctrl.gtxclk_out
reg_eth_rw_gen_ctrl.phyrst_n
reg_eth_rw_tr_ctrl.carrier_ext
- max_size in reg_eth_rw_rec_ctrl had the wrong size.
- Registers reg_eth_rw_mgm_ctrl and reg_eth_r_stat was reworked completely.
Diffstat (limited to 'include/asm-cris')
-rw-r--r-- | include/asm-cris/arch-v32/hwregs/eth_defs.h | 202 |
1 files changed, 98 insertions, 104 deletions
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h index 1196d7cc783f..90fe8a28894f 100644 --- a/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h | |||
@@ -3,12 +3,12 @@ | |||
3 | 3 | ||
4 | /* | 4 | /* |
5 | * This file is autogenerated from | 5 | * This file is autogenerated from |
6 | * file: ../../inst/eth/rtl/eth_regs.r | 6 | * file: eth.r |
7 | * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp | 7 | * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp |
8 | * last modfied: Mon Apr 11 16:07:03 2005 | 8 | * last modfied: Mon Jan 9 06:06:41 2006 |
9 | * | 9 | * |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r | 10 | * by /n/asic/design/tools/rdesc/rdes2c eth.r |
11 | * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | 11 | * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ |
12 | * Any changes here will be lost. | 12 | * Any changes here will be lost. |
13 | * | 13 | * |
14 | * -*- buffer-read-only: t -*- | 14 | * -*- buffer-read-only: t -*- |
@@ -116,26 +116,28 @@ typedef struct { | |||
116 | 116 | ||
117 | /* Register rw_ga_lo, scope eth, type rw */ | 117 | /* Register rw_ga_lo, scope eth, type rw */ |
118 | typedef struct { | 118 | typedef struct { |
119 | unsigned int table : 32; | 119 | unsigned int tbl : 32; |
120 | } reg_eth_rw_ga_lo; | 120 | } reg_eth_rw_ga_lo; |
121 | #define REG_RD_ADDR_eth_rw_ga_lo 16 | 121 | #define REG_RD_ADDR_eth_rw_ga_lo 16 |
122 | #define REG_WR_ADDR_eth_rw_ga_lo 16 | 122 | #define REG_WR_ADDR_eth_rw_ga_lo 16 |
123 | 123 | ||
124 | /* Register rw_ga_hi, scope eth, type rw */ | 124 | /* Register rw_ga_hi, scope eth, type rw */ |
125 | typedef struct { | 125 | typedef struct { |
126 | unsigned int table : 32; | 126 | unsigned int tbl : 32; |
127 | } reg_eth_rw_ga_hi; | 127 | } reg_eth_rw_ga_hi; |
128 | #define REG_RD_ADDR_eth_rw_ga_hi 20 | 128 | #define REG_RD_ADDR_eth_rw_ga_hi 20 |
129 | #define REG_WR_ADDR_eth_rw_ga_hi 20 | 129 | #define REG_WR_ADDR_eth_rw_ga_hi 20 |
130 | 130 | ||
131 | /* Register rw_gen_ctrl, scope eth, type rw */ | 131 | /* Register rw_gen_ctrl, scope eth, type rw */ |
132 | typedef struct { | 132 | typedef struct { |
133 | unsigned int en : 1; | 133 | unsigned int en : 1; |
134 | unsigned int phy : 2; | 134 | unsigned int phy : 2; |
135 | unsigned int protocol : 1; | 135 | unsigned int protocol : 1; |
136 | unsigned int loopback : 1; | 136 | unsigned int loopback : 1; |
137 | unsigned int flow_ctrl_dis : 1; | 137 | unsigned int flow_ctrl : 1; |
138 | unsigned int dummy1 : 26; | 138 | unsigned int gtxclk_out : 1; |
139 | unsigned int phyrst_n : 1; | ||
140 | unsigned int dummy1 : 24; | ||
139 | } reg_eth_rw_gen_ctrl; | 141 | } reg_eth_rw_gen_ctrl; |
140 | #define REG_RD_ADDR_eth_rw_gen_ctrl 24 | 142 | #define REG_RD_ADDR_eth_rw_gen_ctrl 24 |
141 | #define REG_WR_ADDR_eth_rw_gen_ctrl 24 | 143 | #define REG_WR_ADDR_eth_rw_gen_ctrl 24 |
@@ -150,22 +152,23 @@ typedef struct { | |||
150 | unsigned int oversize : 1; | 152 | unsigned int oversize : 1; |
151 | unsigned int bad_crc : 1; | 153 | unsigned int bad_crc : 1; |
152 | unsigned int duplex : 1; | 154 | unsigned int duplex : 1; |
153 | unsigned int max_size : 1; | 155 | unsigned int max_size : 16; |
154 | unsigned int dummy1 : 23; | 156 | unsigned int dummy1 : 8; |
155 | } reg_eth_rw_rec_ctrl; | 157 | } reg_eth_rw_rec_ctrl; |
156 | #define REG_RD_ADDR_eth_rw_rec_ctrl 28 | 158 | #define REG_RD_ADDR_eth_rw_rec_ctrl 28 |
157 | #define REG_WR_ADDR_eth_rw_rec_ctrl 28 | 159 | #define REG_WR_ADDR_eth_rw_rec_ctrl 28 |
158 | 160 | ||
159 | /* Register rw_tr_ctrl, scope eth, type rw */ | 161 | /* Register rw_tr_ctrl, scope eth, type rw */ |
160 | typedef struct { | 162 | typedef struct { |
161 | unsigned int crc : 1; | 163 | unsigned int crc : 1; |
162 | unsigned int pad : 1; | 164 | unsigned int pad : 1; |
163 | unsigned int retry : 1; | 165 | unsigned int retry : 1; |
164 | unsigned int ignore_col : 1; | 166 | unsigned int ignore_col : 1; |
165 | unsigned int cancel : 1; | 167 | unsigned int cancel : 1; |
166 | unsigned int hsh_delay : 1; | 168 | unsigned int hsh_delay : 1; |
167 | unsigned int ignore_crs : 1; | 169 | unsigned int ignore_crs : 1; |
168 | unsigned int dummy1 : 25; | 170 | unsigned int carrier_ext : 1; |
171 | unsigned int dummy1 : 24; | ||
169 | } reg_eth_rw_tr_ctrl; | 172 | } reg_eth_rw_tr_ctrl; |
170 | #define REG_RD_ADDR_eth_rw_tr_ctrl 32 | 173 | #define REG_RD_ADDR_eth_rw_tr_ctrl 32 |
171 | #define REG_WR_ADDR_eth_rw_tr_ctrl 32 | 174 | #define REG_WR_ADDR_eth_rw_tr_ctrl 32 |
@@ -180,13 +183,10 @@ typedef struct { | |||
180 | 183 | ||
181 | /* Register rw_mgm_ctrl, scope eth, type rw */ | 184 | /* Register rw_mgm_ctrl, scope eth, type rw */ |
182 | typedef struct { | 185 | typedef struct { |
183 | unsigned int mdio : 1; | 186 | unsigned int mdio : 1; |
184 | unsigned int mdoe : 1; | 187 | unsigned int mdoe : 1; |
185 | unsigned int mdc : 1; | 188 | unsigned int mdc : 1; |
186 | unsigned int phyclk : 1; | 189 | unsigned int dummy1 : 29; |
187 | unsigned int txdata : 4; | ||
188 | unsigned int txen : 1; | ||
189 | unsigned int dummy1 : 23; | ||
190 | } reg_eth_rw_mgm_ctrl; | 190 | } reg_eth_rw_mgm_ctrl; |
191 | #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 | 191 | #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 |
192 | #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 | 192 | #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 |
@@ -196,17 +196,8 @@ typedef struct { | |||
196 | unsigned int mdio : 1; | 196 | unsigned int mdio : 1; |
197 | unsigned int exc_col : 1; | 197 | unsigned int exc_col : 1; |
198 | unsigned int urun : 1; | 198 | unsigned int urun : 1; |
199 | unsigned int phyclk : 1; | 199 | unsigned int clk_125 : 1; |
200 | unsigned int txdata : 4; | 200 | unsigned int dummy1 : 28; |
201 | unsigned int txen : 1; | ||
202 | unsigned int col : 1; | ||
203 | unsigned int crs : 1; | ||
204 | unsigned int txclk : 1; | ||
205 | unsigned int rxdata : 4; | ||
206 | unsigned int rxer : 1; | ||
207 | unsigned int rxdv : 1; | ||
208 | unsigned int rxclk : 1; | ||
209 | unsigned int dummy1 : 13; | ||
210 | } reg_eth_r_stat; | 201 | } reg_eth_r_stat; |
211 | #define REG_RD_ADDR_eth_r_stat 44 | 202 | #define REG_RD_ADDR_eth_r_stat 44 |
212 | 203 | ||
@@ -274,83 +265,83 @@ typedef struct { | |||
274 | 265 | ||
275 | /* Register rw_intr_mask, scope eth, type rw */ | 266 | /* Register rw_intr_mask, scope eth, type rw */ |
276 | typedef struct { | 267 | typedef struct { |
277 | unsigned int crc : 1; | 268 | unsigned int crc : 1; |
278 | unsigned int align : 1; | 269 | unsigned int align : 1; |
279 | unsigned int oversize : 1; | 270 | unsigned int oversize : 1; |
280 | unsigned int congestion : 1; | 271 | unsigned int congestion : 1; |
281 | unsigned int single_col : 1; | 272 | unsigned int single_col : 1; |
282 | unsigned int mult_col : 1; | 273 | unsigned int mult_col : 1; |
283 | unsigned int late_col : 1; | 274 | unsigned int late_col : 1; |
284 | unsigned int deferred : 1; | 275 | unsigned int deferred : 1; |
285 | unsigned int carrier_loss : 1; | 276 | unsigned int carrier_loss : 1; |
286 | unsigned int sqe_test_err : 1; | 277 | unsigned int sqe_test_err : 1; |
287 | unsigned int orun : 1; | 278 | unsigned int orun : 1; |
288 | unsigned int urun : 1; | 279 | unsigned int urun : 1; |
289 | unsigned int excessive_col : 1; | 280 | unsigned int exc_col : 1; |
290 | unsigned int mdio : 1; | 281 | unsigned int mdio : 1; |
291 | unsigned int dummy1 : 18; | 282 | unsigned int dummy1 : 18; |
292 | } reg_eth_rw_intr_mask; | 283 | } reg_eth_rw_intr_mask; |
293 | #define REG_RD_ADDR_eth_rw_intr_mask 76 | 284 | #define REG_RD_ADDR_eth_rw_intr_mask 76 |
294 | #define REG_WR_ADDR_eth_rw_intr_mask 76 | 285 | #define REG_WR_ADDR_eth_rw_intr_mask 76 |
295 | 286 | ||
296 | /* Register rw_ack_intr, scope eth, type rw */ | 287 | /* Register rw_ack_intr, scope eth, type rw */ |
297 | typedef struct { | 288 | typedef struct { |
298 | unsigned int crc : 1; | 289 | unsigned int crc : 1; |
299 | unsigned int align : 1; | 290 | unsigned int align : 1; |
300 | unsigned int oversize : 1; | 291 | unsigned int oversize : 1; |
301 | unsigned int congestion : 1; | 292 | unsigned int congestion : 1; |
302 | unsigned int single_col : 1; | 293 | unsigned int single_col : 1; |
303 | unsigned int mult_col : 1; | 294 | unsigned int mult_col : 1; |
304 | unsigned int late_col : 1; | 295 | unsigned int late_col : 1; |
305 | unsigned int deferred : 1; | 296 | unsigned int deferred : 1; |
306 | unsigned int carrier_loss : 1; | 297 | unsigned int carrier_loss : 1; |
307 | unsigned int sqe_test_err : 1; | 298 | unsigned int sqe_test_err : 1; |
308 | unsigned int orun : 1; | 299 | unsigned int orun : 1; |
309 | unsigned int urun : 1; | 300 | unsigned int urun : 1; |
310 | unsigned int excessive_col : 1; | 301 | unsigned int exc_col : 1; |
311 | unsigned int mdio : 1; | 302 | unsigned int mdio : 1; |
312 | unsigned int dummy1 : 18; | 303 | unsigned int dummy1 : 18; |
313 | } reg_eth_rw_ack_intr; | 304 | } reg_eth_rw_ack_intr; |
314 | #define REG_RD_ADDR_eth_rw_ack_intr 80 | 305 | #define REG_RD_ADDR_eth_rw_ack_intr 80 |
315 | #define REG_WR_ADDR_eth_rw_ack_intr 80 | 306 | #define REG_WR_ADDR_eth_rw_ack_intr 80 |
316 | 307 | ||
317 | /* Register r_intr, scope eth, type r */ | 308 | /* Register r_intr, scope eth, type r */ |
318 | typedef struct { | 309 | typedef struct { |
319 | unsigned int crc : 1; | 310 | unsigned int crc : 1; |
320 | unsigned int align : 1; | 311 | unsigned int align : 1; |
321 | unsigned int oversize : 1; | 312 | unsigned int oversize : 1; |
322 | unsigned int congestion : 1; | 313 | unsigned int congestion : 1; |
323 | unsigned int single_col : 1; | 314 | unsigned int single_col : 1; |
324 | unsigned int mult_col : 1; | 315 | unsigned int mult_col : 1; |
325 | unsigned int late_col : 1; | 316 | unsigned int late_col : 1; |
326 | unsigned int deferred : 1; | 317 | unsigned int deferred : 1; |
327 | unsigned int carrier_loss : 1; | 318 | unsigned int carrier_loss : 1; |
328 | unsigned int sqe_test_err : 1; | 319 | unsigned int sqe_test_err : 1; |
329 | unsigned int orun : 1; | 320 | unsigned int orun : 1; |
330 | unsigned int urun : 1; | 321 | unsigned int urun : 1; |
331 | unsigned int excessive_col : 1; | 322 | unsigned int exc_col : 1; |
332 | unsigned int mdio : 1; | 323 | unsigned int mdio : 1; |
333 | unsigned int dummy1 : 18; | 324 | unsigned int dummy1 : 18; |
334 | } reg_eth_r_intr; | 325 | } reg_eth_r_intr; |
335 | #define REG_RD_ADDR_eth_r_intr 84 | 326 | #define REG_RD_ADDR_eth_r_intr 84 |
336 | 327 | ||
337 | /* Register r_masked_intr, scope eth, type r */ | 328 | /* Register r_masked_intr, scope eth, type r */ |
338 | typedef struct { | 329 | typedef struct { |
339 | unsigned int crc : 1; | 330 | unsigned int crc : 1; |
340 | unsigned int align : 1; | 331 | unsigned int align : 1; |
341 | unsigned int oversize : 1; | 332 | unsigned int oversize : 1; |
342 | unsigned int congestion : 1; | 333 | unsigned int congestion : 1; |
343 | unsigned int single_col : 1; | 334 | unsigned int single_col : 1; |
344 | unsigned int mult_col : 1; | 335 | unsigned int mult_col : 1; |
345 | unsigned int late_col : 1; | 336 | unsigned int late_col : 1; |
346 | unsigned int deferred : 1; | 337 | unsigned int deferred : 1; |
347 | unsigned int carrier_loss : 1; | 338 | unsigned int carrier_loss : 1; |
348 | unsigned int sqe_test_err : 1; | 339 | unsigned int sqe_test_err : 1; |
349 | unsigned int orun : 1; | 340 | unsigned int orun : 1; |
350 | unsigned int urun : 1; | 341 | unsigned int urun : 1; |
351 | unsigned int excessive_col : 1; | 342 | unsigned int exc_col : 1; |
352 | unsigned int mdio : 1; | 343 | unsigned int mdio : 1; |
353 | unsigned int dummy1 : 18; | 344 | unsigned int dummy1 : 18; |
354 | } reg_eth_r_masked_intr; | 345 | } reg_eth_r_masked_intr; |
355 | #define REG_RD_ADDR_eth_r_masked_intr 88 | 346 | #define REG_RD_ADDR_eth_r_masked_intr 88 |
356 | 347 | ||
@@ -360,12 +351,15 @@ enum { | |||
360 | regk_eth_discard = 0x00000000, | 351 | regk_eth_discard = 0x00000000, |
361 | regk_eth_ether = 0x00000000, | 352 | regk_eth_ether = 0x00000000, |
362 | regk_eth_full = 0x00000001, | 353 | regk_eth_full = 0x00000001, |
354 | regk_eth_gmii = 0x00000003, | ||
355 | regk_eth_gtxclk = 0x00000001, | ||
363 | regk_eth_half = 0x00000000, | 356 | regk_eth_half = 0x00000000, |
364 | regk_eth_hsh = 0x00000001, | 357 | regk_eth_hsh = 0x00000001, |
365 | regk_eth_mii = 0x00000001, | 358 | regk_eth_mii = 0x00000001, |
359 | regk_eth_mii_arec = 0x00000002, | ||
366 | regk_eth_mii_clk = 0x00000000, | 360 | regk_eth_mii_clk = 0x00000000, |
367 | regk_eth_mii_rec = 0x00000002, | ||
368 | regk_eth_no = 0x00000000, | 361 | regk_eth_no = 0x00000000, |
362 | regk_eth_phyrst = 0x00000000, | ||
369 | regk_eth_rec = 0x00000001, | 363 | regk_eth_rec = 0x00000001, |
370 | regk_eth_rw_ga_hi_default = 0x00000000, | 364 | regk_eth_rw_ga_hi_default = 0x00000000, |
371 | regk_eth_rw_ga_lo_default = 0x00000000, | 365 | regk_eth_rw_ga_lo_default = 0x00000000, |
@@ -377,8 +371,8 @@ enum { | |||
377 | regk_eth_rw_ma1_lo_default = 0x00000000, | 371 | regk_eth_rw_ma1_lo_default = 0x00000000, |
378 | regk_eth_rw_mgm_ctrl_default = 0x00000000, | 372 | regk_eth_rw_mgm_ctrl_default = 0x00000000, |
379 | regk_eth_rw_test_ctrl_default = 0x00000000, | 373 | regk_eth_rw_test_ctrl_default = 0x00000000, |
380 | regk_eth_size1518 = 0x00000000, | 374 | regk_eth_size1518 = 0x000005ee, |
381 | regk_eth_size1522 = 0x00000001, | 375 | regk_eth_size1522 = 0x000005f2, |
382 | regk_eth_yes = 0x00000001 | 376 | regk_eth_yes = 0x00000001 |
383 | }; | 377 | }; |
384 | #endif /* __eth_defs_h */ | 378 | #endif /* __eth_defs_h */ |