diff options
author | Robin Getz <robin.getz@analog.com> | 2007-06-20 23:34:16 -0400 |
---|---|---|
committer | Bryan Wu <bryan.wu@analog.com> | 2007-06-20 23:34:16 -0400 |
commit | 4bf3f3cbb6add01d3e6a18c73f594b73113b14f2 (patch) | |
tree | a80839f98a64052f4d004a5207da2731fe556908 /include/asm-blackfin/mach-common/cdef_LPBlackfin.h | |
parent | 0864a4e201b1ea442f4c8b887418a29f67e24d30 (diff) |
Blackfin arch: update ANOMALY handling
update lists for 533, 537, and add SSYNC workaround into assembly files.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-common/cdef_LPBlackfin.h')
-rw-r--r-- | include/asm-blackfin/mach-common/cdef_LPBlackfin.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index d39c396f850d..58f878947cbc 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h | |||
@@ -39,7 +39,20 @@ | |||
39 | #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) | 39 | #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) |
40 | #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) | 40 | #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) |
41 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) | 41 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) |
42 | #ifdef ANOMALY_05000125 | ||
43 | static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val) | ||
44 | { | ||
45 | unsigned long flags, iwr; | ||
46 | |||
47 | local_irq_save(flags); | ||
48 | __asm__(".align 8\n"); | ||
49 | bfin_write32(IMEM_CONTROL, val); | ||
50 | __builtin_bfin_ssync(); | ||
51 | local_irq_restore(flags); | ||
52 | } | ||
53 | #else | ||
42 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) | 54 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) |
55 | #endif | ||
43 | #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) | 56 | #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) |
44 | #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) | 57 | #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) |
45 | #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) | 58 | #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) |
@@ -125,7 +138,21 @@ | |||
125 | #define DTEST_DATA3 0xFFE0040C | 138 | #define DTEST_DATA3 0xFFE0040C |
126 | */ | 139 | */ |
127 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) | 140 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) |
141 | #ifdef ANOMALY_05000125 | ||
142 | static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val) | ||
143 | { | ||
144 | unsigned long flags, iwr; | ||
145 | |||
146 | local_irq_save(flags); | ||
147 | __asm__(".align 8\n"); | ||
148 | bfin_write32(IMEM_CONTROL, val); | ||
149 | __builtin_bfin_ssync(); | ||
150 | local_irq_restore(flags); | ||
151 | |||
152 | } | ||
153 | #else | ||
128 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) | 154 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) |
155 | #endif | ||
129 | #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) | 156 | #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) |
130 | #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) | 157 | #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) |
131 | #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) | 158 | #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) |