diff options
author | David Woodhouse <dwmw2@infradead.org> | 2007-10-13 09:58:23 -0400 |
---|---|---|
committer | David Woodhouse <dwmw2@infradead.org> | 2007-10-13 09:58:23 -0400 |
commit | ebf8889bd1fe3615991ff4494635d237280652a2 (patch) | |
tree | 10fb735717122bbb86474339eac07f26e7ccdf40 /include/asm-blackfin/mach-bf548 | |
parent | b160292cc216a50fd0cd386b0bda2cd48352c73b (diff) | |
parent | 752097cec53eea111d087c545179b421e2bde98a (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r-- | include/asm-blackfin/mach-bf548/anomaly.h | 145 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/bf548.h | 154 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 39 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/blackfin.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 4 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF544.h | 1 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF548.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF549.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF54x_base.h | 3 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/gpio.h | 5 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/irq.h | 591 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/mem_map.h | 24 |
12 files changed, 437 insertions, 535 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index aca1d4ba145c..c5b63759cdee 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h | |||
@@ -1,74 +1,85 @@ | |||
1 | |||
2 | /* | 1 | /* |
3 | * File: include/asm-blackfin/mach-bf548/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
4 | * Based on: | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
5 | * Author: | ||
6 | * | ||
7 | * Created: | ||
8 | * Description: | ||
9 | * | ||
10 | * Rev: | ||
11 | * | ||
12 | * Modified: | ||
13 | * | ||
14 | * | ||
15 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
16 | * | 4 | * |
17 | * This program is free software; you can redistribute it and/or modify | 5 | * Copyright (C) 2004-2007 Analog Devices Inc. |
18 | * it under the terms of the GNU General Public License as published by | 6 | * Licensed under the GPL-2 or later. |
19 | * the Free Software Foundation; either version 2, or (at your option) | 7 | */ |
20 | * any later version. | 8 | |
21 | * | 9 | /* This file shoule be up to date with: |
22 | * This program is distributed in the hope that it will be useful, | 10 | * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
25 | * GNU General Public License for more details. | ||
26 | * | ||
27 | * You should have received a copy of the GNU General Public License | ||
28 | * along with this program; see the file COPYING. | ||
29 | * If not, write to the Free Software Foundation, | ||
30 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
31 | */ | 11 | */ |
32 | 12 | ||
33 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
34 | #define _MACH_ANOMALY_H_ | 14 | #define _MACH_ANOMALY_H_ |
35 | #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | ||
36 | slot1 and store of a P register in slot 2 is not | ||
37 | supported */ | ||
38 | #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive | ||
39 | Channel DMA stops */ | ||
40 | #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR | ||
41 | registers. */ | ||
42 | #define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the | ||
43 | Shadow of a Conditional Branch */ | ||
44 | #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event | ||
45 | interrupt not functional */ | ||
46 | #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | ||
47 | SPORT external receive and transmit clocks. */ | ||
48 | #define ANOMALY_05000272 /* Certain data cache write through modes fail for | ||
49 | VDDint <=0.9V */ | ||
50 | #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is | ||
51 | not restored */ | ||
52 | #define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the | ||
53 | Boundary of Reserved Memory */ | ||
54 | #define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and | ||
55 | LC Registers Are Interrupted */ | ||
56 | #define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ | ||
57 | #define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ | ||
58 | #define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to | ||
59 | the USB FIFO Simultaneously */ | ||
60 | #define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() | ||
61 | function */ | ||
62 | #define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional | ||
63 | */ | ||
64 | #define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ | ||
65 | #define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM | ||
66 | Skew */ | ||
67 | #define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ | ||
68 | #define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration | ||
69 | of Host DMA Port */ | ||
70 | #define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent | ||
71 | Allowed Configuration on Host DMA Port */ | ||
72 | #define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | ||
73 | 15 | ||
74 | #endif /* _MACH_ANOMALY_H_ */ | 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ |
17 | #define ANOMALY_05000074 (1) | ||
18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | ||
19 | #define ANOMALY_05000119 (1) | ||
20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | ||
21 | #define ANOMALY_05000122 (1) | ||
22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | ||
23 | #define ANOMALY_05000245 (1) | ||
24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | ||
25 | #define ANOMALY_05000265 (1) | ||
26 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | ||
27 | #define ANOMALY_05000272 (1) | ||
28 | /* False Hardware Error Exception when ISR context is not restored */ | ||
29 | #define ANOMALY_05000281 (1) | ||
30 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | ||
31 | #define ANOMALY_05000304 (1) | ||
32 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | ||
33 | #define ANOMALY_05000310 (1) | ||
34 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
35 | #define ANOMALY_05000312 (1) | ||
36 | /* TWI Slave Boot Mode Is Not Functional */ | ||
37 | #define ANOMALY_05000324 (1) | ||
38 | /* External FIFO Boot Mode Is Not Functional */ | ||
39 | #define ANOMALY_05000325 (1) | ||
40 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ | ||
41 | #define ANOMALY_05000327 (1) | ||
42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | ||
43 | #define ANOMALY_05000328 (1) | ||
44 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ | ||
45 | #define ANOMALY_05000329 (1) | ||
46 | /* Host DMA Boot Mode Is Not Functional */ | ||
47 | #define ANOMALY_05000330 (1) | ||
48 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ | ||
49 | #define ANOMALY_05000334 (1) | ||
50 | /* Inadequate Rotary Debounce Logic Duration */ | ||
51 | #define ANOMALY_05000335 (1) | ||
52 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ | ||
53 | #define ANOMALY_05000336 (1) | ||
54 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | ||
55 | #define ANOMALY_05000337 (1) | ||
56 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | ||
57 | #define ANOMALY_05000338 (1) | ||
58 | /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ | ||
59 | #define ANOMALY_05000340 (1) | ||
60 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ | ||
61 | #define ANOMALY_05000344 (1) | ||
62 | /* USB Calibration Value Is Not Intialized */ | ||
63 | #define ANOMALY_05000346 (1) | ||
64 | /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ | ||
65 | #define ANOMALY_05000347 (1) | ||
66 | /* Data Lost when Core Reads SDH Data FIFO */ | ||
67 | #define ANOMALY_05000349 (1) | ||
68 | /* PLL Status Register Is Inaccurate */ | ||
69 | #define ANOMALY_05000351 (1) | ||
70 | |||
71 | /* Anomalies that don't exist on this proc */ | ||
72 | #define ANOMALY_05000125 (0) | ||
73 | #define ANOMALY_05000158 (0) | ||
74 | #define ANOMALY_05000183 (0) | ||
75 | #define ANOMALY_05000198 (0) | ||
76 | #define ANOMALY_05000230 (0) | ||
77 | #define ANOMALY_05000244 (0) | ||
78 | #define ANOMALY_05000261 (0) | ||
79 | #define ANOMALY_05000263 (0) | ||
80 | #define ANOMALY_05000266 (0) | ||
81 | #define ANOMALY_05000273 (0) | ||
82 | #define ANOMALY_05000311 (0) | ||
83 | #define ANOMALY_05000323 (0) | ||
84 | |||
85 | #endif | ||
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 9498313a2cb7..7e6d349beb08 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h | |||
@@ -52,12 +52,12 @@ | |||
52 | /***************************/ | 52 | /***************************/ |
53 | 53 | ||
54 | 54 | ||
55 | #define BLKFIN_DSUBBANKS 4 | 55 | #define BFIN_DSUBBANKS 4 |
56 | #define BLKFIN_DWAYS 2 | 56 | #define BFIN_DWAYS 2 |
57 | #define BLKFIN_DLINES 64 | 57 | #define BFIN_DLINES 64 |
58 | #define BLKFIN_ISUBBANKS 4 | 58 | #define BFIN_ISUBBANKS 4 |
59 | #define BLKFIN_IWAYS 4 | 59 | #define BFIN_IWAYS 4 |
60 | #define BLKFIN_ILINES 32 | 60 | #define BFIN_ILINES 32 |
61 | 61 | ||
62 | #define WAY0_L 0x1 | 62 | #define WAY0_L 0x1 |
63 | #define WAY1_L 0x2 | 63 | #define WAY1_L 0x2 |
@@ -106,93 +106,6 @@ | |||
106 | 106 | ||
107 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN) | 107 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN) |
108 | 108 | ||
109 | #define MAX_VC 650000000 | ||
110 | #define MIN_VC 50000000 | ||
111 | |||
112 | /********************************PLL Settings **************************************/ | ||
113 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
114 | #if (CONFIG_VCO_MULT < 0) | ||
115 | #error "VCO Multiplier is less than 0. Please select a different value" | ||
116 | #endif | ||
117 | |||
118 | #if (CONFIG_VCO_MULT == 0) | ||
119 | #error "VCO Multiplier should be greater than 0. Please select a different value" | ||
120 | #endif | ||
121 | |||
122 | #if (CONFIG_VCO_MULT > 64) | ||
123 | #error "VCO Multiplier is more than 64. Please select a different value" | ||
124 | #endif | ||
125 | |||
126 | #ifndef CONFIG_CLKIN_HALF | ||
127 | #define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) | ||
128 | #else | ||
129 | #define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) | ||
130 | #endif | ||
131 | |||
132 | #ifndef CONFIG_PLL_BYPASS | ||
133 | #define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) | ||
134 | #define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) | ||
135 | #else | ||
136 | #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ | ||
137 | #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ | ||
138 | #endif | ||
139 | |||
140 | #if (CONFIG_SCLK_DIV < 1) | ||
141 | #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" | ||
142 | #endif | ||
143 | |||
144 | #if (CONFIG_SCLK_DIV > 15) | ||
145 | #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" | ||
146 | #endif | ||
147 | |||
148 | #if (CONFIG_CCLK_DIV != 1) | ||
149 | #if (CONFIG_CCLK_DIV != 2) | ||
150 | #if (CONFIG_CCLK_DIV != 4) | ||
151 | #if (CONFIG_CCLK_DIV != 8) | ||
152 | #error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" | ||
153 | #endif | ||
154 | #endif | ||
155 | #endif | ||
156 | #endif | ||
157 | |||
158 | #if (CONFIG_VCO_HZ > MAX_VC) | ||
159 | #error "VCO selected is more than maximum value. Please change the VCO multipler" | ||
160 | #endif | ||
161 | |||
162 | #if (CONFIG_SCLK_HZ > 133000000) | ||
163 | #error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" | ||
164 | #endif | ||
165 | |||
166 | #if (CONFIG_SCLK_HZ < 27000000) | ||
167 | #error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" | ||
168 | #endif | ||
169 | |||
170 | #if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) | ||
171 | #if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) | ||
172 | #if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) | ||
173 | #error "Please select sclk less than cclk" | ||
174 | #endif | ||
175 | #endif | ||
176 | #endif | ||
177 | |||
178 | #if (CONFIG_CCLK_DIV == 1) | ||
179 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV1 | ||
180 | #endif | ||
181 | #if (CONFIG_CCLK_DIV == 2) | ||
182 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV2 | ||
183 | #endif | ||
184 | #if (CONFIG_CCLK_DIV == 4) | ||
185 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV4 | ||
186 | #endif | ||
187 | #if (CONFIG_CCLK_DIV == 8) | ||
188 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV8 | ||
189 | #endif | ||
190 | #ifndef CONFIG_CCLK_ACT_DIV | ||
191 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly | ||
192 | #endif | ||
193 | |||
194 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
195 | |||
196 | #ifdef CONFIG_BF542 | 109 | #ifdef CONFIG_BF542 |
197 | #define CPU "BF542" | 110 | #define CPU "BF542" |
198 | #define CPUID 0x027c8000 | 111 | #define CPUID 0x027c8000 |
@@ -213,59 +126,4 @@ | |||
213 | #define CPUID 0x0 | 126 | #define CPUID 0x0 |
214 | #endif | 127 | #endif |
215 | 128 | ||
216 | #if (CONFIG_MEM_SIZE % 4) | ||
217 | #error "SDRAM mem size must be multible of 4MB" | ||
218 | #endif | ||
219 | |||
220 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) | ||
221 | #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) | ||
222 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) | ||
223 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) | ||
224 | |||
225 | /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ | ||
226 | |||
227 | #define ANOMALY_05000158_WORKAROUND 0x200 | ||
228 | #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ | ||
229 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ | ||
230 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | ||
231 | #else /*Write Through */ | ||
232 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ | ||
233 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) | ||
234 | #endif | ||
235 | |||
236 | |||
237 | #define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) | ||
238 | #define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) | ||
239 | #define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) | ||
240 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) | ||
241 | |||
242 | #define SIZE_1K 0x00000400 /* 1K */ | ||
243 | #define SIZE_4K 0x00001000 /* 4K */ | ||
244 | #define SIZE_1M 0x00100000 /* 1M */ | ||
245 | #define SIZE_4M 0x00400000 /* 4M */ | ||
246 | |||
247 | #define MAX_CPLBS (16 * 2) | ||
248 | |||
249 | /* | ||
250 | * Number of required data CPLB switchtable entries | ||
251 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
252 | * approx 16 for smaller 1MB page size CPLBs for allignment purposes | ||
253 | * 1 for L1 Data Memory | ||
254 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
255 | * 1 for ASYNC Memory | ||
256 | */ | ||
257 | |||
258 | |||
259 | #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) | ||
260 | |||
261 | /* | ||
262 | * Number of required instruction CPLB switchtable entries | ||
263 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
264 | * approx 12 for smaller 1MB page size CPLBs for allignment purposes | ||
265 | * 1 for L1 Instruction Memory | ||
266 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
267 | */ | ||
268 | |||
269 | #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) | ||
270 | |||
271 | #endif /* __MACH_BF48_H__ */ | 129 | #endif /* __MACH_BF48_H__ */ |
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 2f4afc90db11..f21a1620e6bd 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | |||
@@ -1,5 +1,6 @@ | |||
1 | #include <linux/serial.h> | 1 | #include <linux/serial.h> |
2 | #include <asm/dma.h> | 2 | #include <asm/dma.h> |
3 | #include <asm/portmux.h> | ||
3 | 4 | ||
4 | #define NR_PORTS 4 | 5 | #define NR_PORTS 4 |
5 | 6 | ||
@@ -143,50 +144,48 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
143 | 144 | ||
144 | int nr_ports = ARRAY_SIZE(bfin_serial_resource); | 145 | int nr_ports = ARRAY_SIZE(bfin_serial_resource); |
145 | 146 | ||
147 | #define DRIVER_NAME "bfin-uart" | ||
148 | |||
146 | static void bfin_serial_hw_init(struct bfin_serial_port *uart) | 149 | static void bfin_serial_hw_init(struct bfin_serial_port *uart) |
147 | { | 150 | { |
148 | #ifdef CONFIG_SERIAL_BFIN_UART0 | 151 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
149 | /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */ | 152 | peripheral_request(P_UART0_TX, DRIVER_NAME); |
150 | bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER()); | 153 | peripheral_request(P_UART0_RX, DRIVER_NAME); |
151 | bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX()); | ||
152 | #endif | 154 | #endif |
153 | 155 | ||
154 | #ifdef CONFIG_SERIAL_BFIN_UART1 | 156 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
155 | /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */ | 157 | peripheral_request(P_UART1_TX, DRIVER_NAME); |
156 | bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER()); | 158 | peripheral_request(P_UART1_RX, DRIVER_NAME); |
157 | bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX()); | 159 | |
158 | #ifdef CONFIG_BFIN_UART1_CTSRTS | 160 | #ifdef CONFIG_BFIN_UART1_CTSRTS |
159 | /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */ | 161 | peripheral_request(P_UART1_RTS, DRIVER_NAME); |
160 | bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER()); | 162 | peripheral_request(P_UART1_CTS DRIVER_NAME); |
161 | bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX()); | ||
162 | #endif | 163 | #endif |
163 | #endif | 164 | #endif |
164 | 165 | ||
165 | #ifdef CONFIG_SERIAL_BFIN_UART2 | 166 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
166 | /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */ | 167 | peripheral_request(P_UART2_TX, DRIVER_NAME); |
167 | bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER()); | 168 | peripheral_request(P_UART2_RX, DRIVER_NAME); |
168 | bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX()); | ||
169 | #endif | 169 | #endif |
170 | 170 | ||
171 | #ifdef CONFIG_SERIAL_BFIN_UART3 | 171 | #ifdef CONFIG_SERIAL_BFIN_UART3 |
172 | /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */ | 172 | peripheral_request(P_UART3_TX, DRIVER_NAME); |
173 | bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER()); | 173 | peripheral_request(P_UART3_RX, DRIVER_NAME); |
174 | bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX()); | 174 | |
175 | #ifdef CONFIG_BFIN_UART3_CTSRTS | 175 | #ifdef CONFIG_BFIN_UART3_CTSRTS |
176 | /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */ | 176 | peripheral_request(P_UART3_RTS, DRIVER_NAME); |
177 | bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER()); | 177 | peripheral_request(P_UART3_CTS DRIVER_NAME); |
178 | bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX()); | ||
179 | #endif | 178 | #endif |
180 | #endif | 179 | #endif |
181 | SSYNC(); | 180 | SSYNC(); |
182 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | 181 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
183 | if (uart->cts_pin >= 0) { | 182 | if (uart->cts_pin >= 0) { |
184 | gpio_request(uart->cts_pin, NULL); | 183 | gpio_request(uart->cts_pin, DRIVER_NAME); |
185 | gpio_direction_input(uart->cts_pin); | 184 | gpio_direction_input(uart->cts_pin); |
186 | } | 185 | } |
187 | 186 | ||
188 | if (uart->rts_pin >= 0) { | 187 | if (uart->rts_pin >= 0) { |
189 | gpio_request(uart->rts_pin, NULL); | 188 | gpio_request(uart->rts_pin, DRIVER_NAME); |
190 | gpio_direction_output(uart->rts_pin); | 189 | gpio_direction_output(uart->rts_pin); |
191 | } | 190 | } |
192 | #endif | 191 | #endif |
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 791218fe7d94..19e84dd4c99c 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h | |||
@@ -54,7 +54,7 @@ | |||
54 | #include "defBF549.h" | 54 | #include "defBF549.h" |
55 | #endif | 55 | #endif |
56 | 56 | ||
57 | #if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) | 57 | #if !defined(__ASSEMBLY__) |
58 | #ifdef CONFIG_BF542 | 58 | #ifdef CONFIG_BF542 |
59 | #include "cdefBF542.h" | 59 | #include "cdefBF542.h" |
60 | #endif | 60 | #endif |
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index cdf29e75ea59..aefab3f618c1 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h | |||
@@ -31,6 +31,8 @@ | |||
31 | #ifndef _CDEF_BF54X_H | 31 | #ifndef _CDEF_BF54X_H |
32 | #define _CDEF_BF54X_H | 32 | #define _CDEF_BF54X_H |
33 | 33 | ||
34 | #include <asm/blackfin.h> | ||
35 | |||
34 | #include "defBF54x_base.h" | 36 | #include "defBF54x_base.h" |
35 | #include <asm/system.h> | 37 | #include <asm/system.h> |
36 | 38 | ||
@@ -60,7 +62,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
60 | bfin_write32(SIC_IWR2, 0); | 62 | bfin_write32(SIC_IWR2, 0); |
61 | 63 | ||
62 | bfin_write16(VR_CTL, val); | 64 | bfin_write16(VR_CTL, val); |
63 | __builtin_bfin_ssync(); | 65 | SSYNC(); |
64 | 66 | ||
65 | local_irq_save(flags); | 67 | local_irq_save(flags); |
66 | asm("IDLE;"); | 68 | asm("IDLE;"); |
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index dd955dcd39b8..760307e34b9e 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h | |||
@@ -81,6 +81,7 @@ | |||
81 | 81 | ||
82 | /* Two Wire Interface Registers (TWI1) */ | 82 | /* Two Wire Interface Registers (TWI1) */ |
83 | 83 | ||
84 | #define TWI1_REGBASE 0xffc02200 | ||
84 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | 85 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
85 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | 86 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
86 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | 87 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ |
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index 8d4214e0807c..70af33c963b0 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h | |||
@@ -120,6 +120,7 @@ | |||
120 | 120 | ||
121 | /* Two Wire Interface Registers (TWI1) */ | 121 | /* Two Wire Interface Registers (TWI1) */ |
122 | 122 | ||
123 | #define TWI1_REGBASE 0xffc02200 | ||
123 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | 124 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
124 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | 125 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
125 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | 126 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ |
@@ -139,6 +140,7 @@ | |||
139 | 140 | ||
140 | /* SPI2 Registers */ | 141 | /* SPI2 Registers */ |
141 | 142 | ||
143 | #define SPI2_REGBASE 0xffc02400 | ||
142 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ | 144 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ |
143 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ | 145 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ |
144 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ | 146 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ |
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index c2f4734da48d..50b3fe55ef0c 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h | |||
@@ -121,6 +121,7 @@ | |||
121 | 121 | ||
122 | /* Two Wire Interface Registers (TWI1) */ | 122 | /* Two Wire Interface Registers (TWI1) */ |
123 | 123 | ||
124 | #define TWI1_REGBASE 0xffc02200 | ||
124 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | 125 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
125 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | 126 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
126 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | 127 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ |
@@ -140,6 +141,7 @@ | |||
140 | 141 | ||
141 | /* SPI2 Registers */ | 142 | /* SPI2 Registers */ |
142 | 143 | ||
144 | #define SPI2_REGBASE 0xffc02400 | ||
143 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ | 145 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ |
144 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ | 146 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ |
145 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ | 147 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ |
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 895ddd40a838..e2632db74baa 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h | |||
@@ -109,6 +109,7 @@ | |||
109 | 109 | ||
110 | /* SPI0 Registers */ | 110 | /* SPI0 Registers */ |
111 | 111 | ||
112 | #define SPI0_REGBASE 0xffc00500 | ||
112 | #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ | 113 | #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ |
113 | #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ | 114 | #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ |
114 | #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ | 115 | #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ |
@@ -121,6 +122,7 @@ | |||
121 | 122 | ||
122 | /* Two Wire Interface Registers (TWI0) */ | 123 | /* Two Wire Interface Registers (TWI0) */ |
123 | 124 | ||
125 | #define TWI0_REGBASE 0xffc00700 | ||
124 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ | 126 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ |
125 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ | 127 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ |
126 | #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ | 128 | #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ |
@@ -978,6 +980,7 @@ | |||
978 | 980 | ||
979 | /* SPI1 Registers */ | 981 | /* SPI1 Registers */ |
980 | 982 | ||
983 | #define SPI1_REGBASE 0xffc02300 | ||
981 | #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ | 984 | #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ |
982 | #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ | 985 | #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ |
983 | #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ | 986 | #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ |
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h index dbf66bcabe35..cb8b0f15c9a6 100644 --- a/include/asm-blackfin/mach-bf548/gpio.h +++ b/include/asm-blackfin/mach-bf548/gpio.h | |||
@@ -209,8 +209,3 @@ struct gpio_port_t { | |||
209 | unsigned short dummy7; | 209 | unsigned short dummy7; |
210 | unsigned int port_mux; | 210 | unsigned int port_mux; |
211 | }; | 211 | }; |
212 | |||
213 | int gpio_request(unsigned short gpio, const char *label); | ||
214 | void peripheral_free(unsigned short per); | ||
215 | int peripheral_request_list(unsigned short per[], const char *label); | ||
216 | void peripheral_free_list(unsigned short per[]); | ||
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index e548d3cd81e3..3b08cf9bd6f3 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h | |||
@@ -55,287 +55,288 @@ Events (highest priority) EMU 0 | |||
55 | 55 | ||
56 | /* The ABSTRACT IRQ definitions */ | 56 | /* The ABSTRACT IRQ definitions */ |
57 | /** the first seven of the following are fixed, the rest you change if you need to **/ | 57 | /** the first seven of the following are fixed, the rest you change if you need to **/ |
58 | #define IRQ_EMU 0 /* Emulation */ | 58 | #define IRQ_EMU 0 /* Emulation */ |
59 | #define IRQ_RST 1 /* reset */ | 59 | #define IRQ_RST 1 /* reset */ |
60 | #define IRQ_NMI 2 /* Non Maskable */ | 60 | #define IRQ_NMI 2 /* Non Maskable */ |
61 | #define IRQ_EVX 3 /* Exception */ | 61 | #define IRQ_EVX 3 /* Exception */ |
62 | #define IRQ_UNUSED 4 /* - unused interrupt*/ | 62 | #define IRQ_UNUSED 4 /* - unused interrupt*/ |
63 | #define IRQ_HWERR 5 /* Hardware Error */ | 63 | #define IRQ_HWERR 5 /* Hardware Error */ |
64 | #define IRQ_CORETMR 6 /* Core timer */ | 64 | #define IRQ_CORETMR 6 /* Core timer */ |
65 | 65 | ||
66 | #define BFIN_IRQ(x) ((x) + 7) | 66 | #define BFIN_IRQ(x) ((x) + 7) |
67 | 67 | ||
68 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ | 68 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ |
69 | #define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ | 69 | #define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ |
70 | #define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ | 70 | #define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ |
71 | #define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ | 71 | #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ |
72 | #define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ | 72 | #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ |
73 | #define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ | 73 | #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ |
74 | #define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ | 74 | #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ |
75 | #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ | 75 | #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ |
76 | #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ | 76 | #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ |
77 | #define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ | 77 | #define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ |
78 | #define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ | 78 | #define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ |
79 | #define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ | 79 | #define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ |
80 | #define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ | 80 | #define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ |
81 | #define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ | 81 | #define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ |
82 | #define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ | 82 | #define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ |
83 | #define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ | 83 | #define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ |
84 | #define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ | 84 | #define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ |
85 | #define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ | 85 | #define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ |
86 | #define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ | 86 | #define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ |
87 | #define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ | 87 | #define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ |
88 | #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ | 88 | #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ |
89 | #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ | 89 | #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ |
90 | #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ | 90 | #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ |
91 | #define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ | 91 | #define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ |
92 | #define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ | 92 | #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ |
93 | #define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ | 93 | #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ |
94 | #define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ | 94 | #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ |
95 | #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ | 95 | #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ |
96 | #define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ | 96 | #define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ |
97 | #define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ | 97 | #define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ |
98 | #define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ | 98 | #define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ |
99 | #define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ | 99 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ |
100 | #define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ | 100 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ |
101 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ | 101 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ |
102 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ | 102 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ |
103 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ | 103 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ |
104 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ | 104 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ |
105 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ | 105 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ |
106 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ | 106 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ |
107 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ | 107 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ |
108 | #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ | 108 | #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ |
109 | #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ | 109 | #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ |
110 | #define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ | 110 | #define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ |
111 | #define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ | 111 | #define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ |
112 | #define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ | 112 | #define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ |
113 | #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ | 113 | #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ |
114 | #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ | 114 | #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ |
115 | #define IRQ_TWI IRQ_TWI0 /* TWI Interrupt */ | 115 | #define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ |
116 | #define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ | 116 | #define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ |
117 | #define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ | 117 | #define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ |
118 | #define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ | 118 | #define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ |
119 | #define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ | 119 | #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ |
120 | #define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ | 120 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ |
121 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ | 121 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ |
122 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ | 122 | #define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ |
123 | #define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ | 123 | #define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ |
124 | #define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ | 124 | #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ |
125 | #define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ | 125 | #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ |
126 | #define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ | 126 | #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ |
127 | #define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ | 127 | #define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */ |
128 | #define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */ | 128 | #define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */ |
129 | #define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */ | 129 | #define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ |
130 | #define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ | 130 | #define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ |
131 | #define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ | 131 | #define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ |
132 | #define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ | 132 | #define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ |
133 | #define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ | 133 | #define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ |
134 | #define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ | 134 | #define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ |
135 | #define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ | 135 | #define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ |
136 | #define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ | 136 | #define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ |
137 | #define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ | 137 | #define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ |
138 | #define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ | 138 | #define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ |
139 | #define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ | 139 | #define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ |
140 | #define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ | 140 | #define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ |
141 | #define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ | 141 | #define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ |
142 | #define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ | 142 | #define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ |
143 | #define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ | 143 | #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ |
144 | #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ | 144 | #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ |
145 | #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ | 145 | #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ |
146 | #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ | 146 | #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ |
147 | #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ | 147 | #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ |
148 | #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ | 148 | #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ |
149 | #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ | 149 | #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ |
150 | #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ | 150 | #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ |
151 | #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ | 151 | #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ |
152 | #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ | 152 | #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ |
153 | #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ | 153 | #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ |
154 | #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ | 154 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ |
155 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ | 155 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ |
156 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ | 156 | |
157 | 157 | #define SYS_IRQS IRQ_PINT3 | |
158 | #define SYS_IRQS IRQ_PINT3 | 158 | |
159 | 159 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) | |
160 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) | 160 | #define IRQ_PA0 BFIN_PA_IRQ(0) |
161 | #define IRQ_PA0 BFIN_PA_IRQ(0) | 161 | #define IRQ_PA1 BFIN_PA_IRQ(1) |
162 | #define IRQ_PA1 BFIN_PA_IRQ(1) | 162 | #define IRQ_PA2 BFIN_PA_IRQ(2) |
163 | #define IRQ_PA2 BFIN_PA_IRQ(2) | 163 | #define IRQ_PA3 BFIN_PA_IRQ(3) |
164 | #define IRQ_PA3 BFIN_PA_IRQ(3) | 164 | #define IRQ_PA4 BFIN_PA_IRQ(4) |
165 | #define IRQ_PA4 BFIN_PA_IRQ(4) | 165 | #define IRQ_PA5 BFIN_PA_IRQ(5) |
166 | #define IRQ_PA5 BFIN_PA_IRQ(5) | 166 | #define IRQ_PA6 BFIN_PA_IRQ(6) |
167 | #define IRQ_PA6 BFIN_PA_IRQ(6) | 167 | #define IRQ_PA7 BFIN_PA_IRQ(7) |
168 | #define IRQ_PA7 BFIN_PA_IRQ(7) | 168 | #define IRQ_PA8 BFIN_PA_IRQ(8) |
169 | #define IRQ_PA8 BFIN_PA_IRQ(8) | 169 | #define IRQ_PA9 BFIN_PA_IRQ(9) |
170 | #define IRQ_PA9 BFIN_PA_IRQ(9) | 170 | #define IRQ_PA10 BFIN_PA_IRQ(10) |
171 | #define IRQ_PA10 BFIN_PA_IRQ(10) | 171 | #define IRQ_PA11 BFIN_PA_IRQ(11) |
172 | #define IRQ_PA11 BFIN_PA_IRQ(11) | 172 | #define IRQ_PA12 BFIN_PA_IRQ(12) |
173 | #define IRQ_PA12 BFIN_PA_IRQ(12) | 173 | #define IRQ_PA13 BFIN_PA_IRQ(13) |
174 | #define IRQ_PA13 BFIN_PA_IRQ(13) | 174 | #define IRQ_PA14 BFIN_PA_IRQ(14) |
175 | #define IRQ_PA14 BFIN_PA_IRQ(14) | 175 | #define IRQ_PA15 BFIN_PA_IRQ(15) |
176 | #define IRQ_PA15 BFIN_PA_IRQ(15) | 176 | |
177 | 177 | #define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) | |
178 | #define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) | 178 | #define IRQ_PB0 BFIN_PB_IRQ(0) |
179 | #define IRQ_PB0 BFIN_PB_IRQ(0) | 179 | #define IRQ_PB1 BFIN_PB_IRQ(1) |
180 | #define IRQ_PB1 BFIN_PB_IRQ(1) | 180 | #define IRQ_PB2 BFIN_PB_IRQ(2) |
181 | #define IRQ_PB2 BFIN_PB_IRQ(2) | 181 | #define IRQ_PB3 BFIN_PB_IRQ(3) |
182 | #define IRQ_PB3 BFIN_PB_IRQ(3) | 182 | #define IRQ_PB4 BFIN_PB_IRQ(4) |
183 | #define IRQ_PB4 BFIN_PB_IRQ(4) | 183 | #define IRQ_PB5 BFIN_PB_IRQ(5) |
184 | #define IRQ_PB5 BFIN_PB_IRQ(5) | 184 | #define IRQ_PB6 BFIN_PB_IRQ(6) |
185 | #define IRQ_PB6 BFIN_PB_IRQ(6) | 185 | #define IRQ_PB7 BFIN_PB_IRQ(7) |
186 | #define IRQ_PB7 BFIN_PB_IRQ(7) | 186 | #define IRQ_PB8 BFIN_PB_IRQ(8) |
187 | #define IRQ_PB8 BFIN_PB_IRQ(8) | 187 | #define IRQ_PB9 BFIN_PB_IRQ(9) |
188 | #define IRQ_PB9 BFIN_PB_IRQ(9) | 188 | #define IRQ_PB10 BFIN_PB_IRQ(10) |
189 | #define IRQ_PB10 BFIN_PB_IRQ(10) | 189 | #define IRQ_PB11 BFIN_PB_IRQ(11) |
190 | #define IRQ_PB11 BFIN_PB_IRQ(11) | 190 | #define IRQ_PB12 BFIN_PB_IRQ(12) |
191 | #define IRQ_PB12 BFIN_PB_IRQ(12) | 191 | #define IRQ_PB13 BFIN_PB_IRQ(13) |
192 | #define IRQ_PB13 BFIN_PB_IRQ(13) | 192 | #define IRQ_PB14 BFIN_PB_IRQ(14) |
193 | #define IRQ_PB14 BFIN_PB_IRQ(14) | 193 | #define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ |
194 | #define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ | 194 | |
195 | 195 | #define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) | |
196 | #define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) | 196 | #define IRQ_PC0 BFIN_PC_IRQ(0) |
197 | #define IRQ_PC0 BFIN_PC_IRQ(0) | 197 | #define IRQ_PC1 BFIN_PC_IRQ(1) |
198 | #define IRQ_PC1 BFIN_PC_IRQ(1) | 198 | #define IRQ_PC2 BFIN_PC_IRQ(2) |
199 | #define IRQ_PC2 BFIN_PC_IRQ(2) | 199 | #define IRQ_PC3 BFIN_PC_IRQ(3) |
200 | #define IRQ_PC3 BFIN_PC_IRQ(3) | 200 | #define IRQ_PC4 BFIN_PC_IRQ(4) |
201 | #define IRQ_PC4 BFIN_PC_IRQ(4) | 201 | #define IRQ_PC5 BFIN_PC_IRQ(5) |
202 | #define IRQ_PC5 BFIN_PC_IRQ(5) | 202 | #define IRQ_PC6 BFIN_PC_IRQ(6) |
203 | #define IRQ_PC6 BFIN_PC_IRQ(6) | 203 | #define IRQ_PC7 BFIN_PC_IRQ(7) |
204 | #define IRQ_PC7 BFIN_PC_IRQ(7) | 204 | #define IRQ_PC8 BFIN_PC_IRQ(8) |
205 | #define IRQ_PC8 BFIN_PC_IRQ(8) | 205 | #define IRQ_PC9 BFIN_PC_IRQ(9) |
206 | #define IRQ_PC9 BFIN_PC_IRQ(9) | 206 | #define IRQ_PC10 BFIN_PC_IRQ(10) |
207 | #define IRQ_PC10 BFIN_PC_IRQ(10) | 207 | #define IRQ_PC11 BFIN_PC_IRQ(11) |
208 | #define IRQ_PC11 BFIN_PC_IRQ(11) | 208 | #define IRQ_PC12 BFIN_PC_IRQ(12) |
209 | #define IRQ_PC12 BFIN_PC_IRQ(12) | 209 | #define IRQ_PC13 BFIN_PC_IRQ(13) |
210 | #define IRQ_PC13 BFIN_PC_IRQ(13) | 210 | #define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ |
211 | #define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ | 211 | #define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ |
212 | #define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ | 212 | |
213 | 213 | #define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) | |
214 | #define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) | 214 | #define IRQ_PD0 BFIN_PD_IRQ(0) |
215 | #define IRQ_PD0 BFIN_PD_IRQ(0) | 215 | #define IRQ_PD1 BFIN_PD_IRQ(1) |
216 | #define IRQ_PD1 BFIN_PD_IRQ(1) | 216 | #define IRQ_PD2 BFIN_PD_IRQ(2) |
217 | #define IRQ_PD2 BFIN_PD_IRQ(2) | 217 | #define IRQ_PD3 BFIN_PD_IRQ(3) |
218 | #define IRQ_PD3 BFIN_PD_IRQ(3) | 218 | #define IRQ_PD4 BFIN_PD_IRQ(4) |
219 | #define IRQ_PD4 BFIN_PD_IRQ(4) | 219 | #define IRQ_PD5 BFIN_PD_IRQ(5) |
220 | #define IRQ_PD5 BFIN_PD_IRQ(5) | 220 | #define IRQ_PD6 BFIN_PD_IRQ(6) |
221 | #define IRQ_PD6 BFIN_PD_IRQ(6) | 221 | #define IRQ_PD7 BFIN_PD_IRQ(7) |
222 | #define IRQ_PD7 BFIN_PD_IRQ(7) | 222 | #define IRQ_PD8 BFIN_PD_IRQ(8) |
223 | #define IRQ_PD8 BFIN_PD_IRQ(8) | 223 | #define IRQ_PD9 BFIN_PD_IRQ(9) |
224 | #define IRQ_PD9 BFIN_PD_IRQ(9) | 224 | #define IRQ_PD10 BFIN_PD_IRQ(10) |
225 | #define IRQ_PD10 BFIN_PD_IRQ(10) | 225 | #define IRQ_PD11 BFIN_PD_IRQ(11) |
226 | #define IRQ_PD11 BFIN_PD_IRQ(11) | 226 | #define IRQ_PD12 BFIN_PD_IRQ(12) |
227 | #define IRQ_PD12 BFIN_PD_IRQ(12) | 227 | #define IRQ_PD13 BFIN_PD_IRQ(13) |
228 | #define IRQ_PD13 BFIN_PD_IRQ(13) | 228 | #define IRQ_PD14 BFIN_PD_IRQ(14) |
229 | #define IRQ_PD14 BFIN_PD_IRQ(14) | 229 | #define IRQ_PD15 BFIN_PD_IRQ(15) |
230 | #define IRQ_PD15 BFIN_PD_IRQ(15) | 230 | |
231 | 231 | #define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) | |
232 | #define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) | 232 | #define IRQ_PE0 BFIN_PE_IRQ(0) |
233 | #define IRQ_PE0 BFIN_PE_IRQ(0) | 233 | #define IRQ_PE1 BFIN_PE_IRQ(1) |
234 | #define IRQ_PE1 BFIN_PE_IRQ(1) | 234 | #define IRQ_PE2 BFIN_PE_IRQ(2) |
235 | #define IRQ_PE2 BFIN_PE_IRQ(2) | 235 | #define IRQ_PE3 BFIN_PE_IRQ(3) |
236 | #define IRQ_PE3 BFIN_PE_IRQ(3) | 236 | #define IRQ_PE4 BFIN_PE_IRQ(4) |
237 | #define IRQ_PE4 BFIN_PE_IRQ(4) | 237 | #define IRQ_PE5 BFIN_PE_IRQ(5) |
238 | #define IRQ_PE5 BFIN_PE_IRQ(5) | 238 | #define IRQ_PE6 BFIN_PE_IRQ(6) |
239 | #define IRQ_PE6 BFIN_PE_IRQ(6) | 239 | #define IRQ_PE7 BFIN_PE_IRQ(7) |
240 | #define IRQ_PE7 BFIN_PE_IRQ(7) | 240 | #define IRQ_PE8 BFIN_PE_IRQ(8) |
241 | #define IRQ_PE8 BFIN_PE_IRQ(8) | 241 | #define IRQ_PE9 BFIN_PE_IRQ(9) |
242 | #define IRQ_PE9 BFIN_PE_IRQ(9) | 242 | #define IRQ_PE10 BFIN_PE_IRQ(10) |
243 | #define IRQ_PE10 BFIN_PE_IRQ(10) | 243 | #define IRQ_PE11 BFIN_PE_IRQ(11) |
244 | #define IRQ_PE11 BFIN_PE_IRQ(11) | 244 | #define IRQ_PE12 BFIN_PE_IRQ(12) |
245 | #define IRQ_PE12 BFIN_PE_IRQ(12) | 245 | #define IRQ_PE13 BFIN_PE_IRQ(13) |
246 | #define IRQ_PE13 BFIN_PE_IRQ(13) | 246 | #define IRQ_PE14 BFIN_PE_IRQ(14) |
247 | #define IRQ_PE14 BFIN_PE_IRQ(14) | 247 | #define IRQ_PE15 BFIN_PE_IRQ(15) |
248 | #define IRQ_PE15 BFIN_PE_IRQ(15) | 248 | |
249 | 249 | #define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) | |
250 | #define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) | 250 | #define IRQ_PF0 BFIN_PF_IRQ(0) |
251 | #define IRQ_PF0 BFIN_PF_IRQ(0) | 251 | #define IRQ_PF1 BFIN_PF_IRQ(1) |
252 | #define IRQ_PF1 BFIN_PF_IRQ(1) | 252 | #define IRQ_PF2 BFIN_PF_IRQ(2) |
253 | #define IRQ_PF2 BFIN_PF_IRQ(2) | 253 | #define IRQ_PF3 BFIN_PF_IRQ(3) |
254 | #define IRQ_PF3 BFIN_PF_IRQ(3) | 254 | #define IRQ_PF4 BFIN_PF_IRQ(4) |
255 | #define IRQ_PF4 BFIN_PF_IRQ(4) | 255 | #define IRQ_PF5 BFIN_PF_IRQ(5) |
256 | #define IRQ_PF5 BFIN_PF_IRQ(5) | 256 | #define IRQ_PF6 BFIN_PF_IRQ(6) |
257 | #define IRQ_PF6 BFIN_PF_IRQ(6) | 257 | #define IRQ_PF7 BFIN_PF_IRQ(7) |
258 | #define IRQ_PF7 BFIN_PF_IRQ(7) | 258 | #define IRQ_PF8 BFIN_PF_IRQ(8) |
259 | #define IRQ_PF8 BFIN_PF_IRQ(8) | 259 | #define IRQ_PF9 BFIN_PF_IRQ(9) |
260 | #define IRQ_PF9 BFIN_PF_IRQ(9) | 260 | #define IRQ_PF10 BFIN_PF_IRQ(10) |
261 | #define IRQ_PF10 BFIN_PF_IRQ(10) | 261 | #define IRQ_PF11 BFIN_PF_IRQ(11) |
262 | #define IRQ_PF11 BFIN_PF_IRQ(11) | 262 | #define IRQ_PF12 BFIN_PF_IRQ(12) |
263 | #define IRQ_PF12 BFIN_PF_IRQ(12) | 263 | #define IRQ_PF13 BFIN_PF_IRQ(13) |
264 | #define IRQ_PF13 BFIN_PF_IRQ(13) | 264 | #define IRQ_PF14 BFIN_PF_IRQ(14) |
265 | #define IRQ_PF14 BFIN_PF_IRQ(14) | 265 | #define IRQ_PF15 BFIN_PF_IRQ(15) |
266 | #define IRQ_PF15 BFIN_PF_IRQ(15) | 266 | |
267 | 267 | #define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) | |
268 | #define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) | 268 | #define IRQ_PG0 BFIN_PG_IRQ(0) |
269 | #define IRQ_PG0 BFIN_PG_IRQ(0) | 269 | #define IRQ_PG1 BFIN_PG_IRQ(1) |
270 | #define IRQ_PG1 BFIN_PG_IRQ(1) | 270 | #define IRQ_PG2 BFIN_PG_IRQ(2) |
271 | #define IRQ_PG2 BFIN_PG_IRQ(2) | 271 | #define IRQ_PG3 BFIN_PG_IRQ(3) |
272 | #define IRQ_PG3 BFIN_PG_IRQ(3) | 272 | #define IRQ_PG4 BFIN_PG_IRQ(4) |
273 | #define IRQ_PG4 BFIN_PG_IRQ(4) | 273 | #define IRQ_PG5 BFIN_PG_IRQ(5) |
274 | #define IRQ_PG5 BFIN_PG_IRQ(5) | 274 | #define IRQ_PG6 BFIN_PG_IRQ(6) |
275 | #define IRQ_PG6 BFIN_PG_IRQ(6) | 275 | #define IRQ_PG7 BFIN_PG_IRQ(7) |
276 | #define IRQ_PG7 BFIN_PG_IRQ(7) | 276 | #define IRQ_PG8 BFIN_PG_IRQ(8) |
277 | #define IRQ_PG8 BFIN_PG_IRQ(8) | 277 | #define IRQ_PG9 BFIN_PG_IRQ(9) |
278 | #define IRQ_PG9 BFIN_PG_IRQ(9) | 278 | #define IRQ_PG10 BFIN_PG_IRQ(10) |
279 | #define IRQ_PG10 BFIN_PG_IRQ(10) | 279 | #define IRQ_PG11 BFIN_PG_IRQ(11) |
280 | #define IRQ_PG11 BFIN_PG_IRQ(11) | 280 | #define IRQ_PG12 BFIN_PG_IRQ(12) |
281 | #define IRQ_PG12 BFIN_PG_IRQ(12) | 281 | #define IRQ_PG13 BFIN_PG_IRQ(13) |
282 | #define IRQ_PG13 BFIN_PG_IRQ(13) | 282 | #define IRQ_PG14 BFIN_PG_IRQ(14) |
283 | #define IRQ_PG14 BFIN_PG_IRQ(14) | 283 | #define IRQ_PG15 BFIN_PG_IRQ(15) |
284 | #define IRQ_PG15 BFIN_PG_IRQ(15) | 284 | |
285 | 285 | #define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) | |
286 | #define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) | 286 | #define IRQ_PH0 BFIN_PH_IRQ(0) |
287 | #define IRQ_PH0 BFIN_PH_IRQ(0) | 287 | #define IRQ_PH1 BFIN_PH_IRQ(1) |
288 | #define IRQ_PH1 BFIN_PH_IRQ(1) | 288 | #define IRQ_PH2 BFIN_PH_IRQ(2) |
289 | #define IRQ_PH2 BFIN_PH_IRQ(2) | 289 | #define IRQ_PH3 BFIN_PH_IRQ(3) |
290 | #define IRQ_PH3 BFIN_PH_IRQ(3) | 290 | #define IRQ_PH4 BFIN_PH_IRQ(4) |
291 | #define IRQ_PH4 BFIN_PH_IRQ(4) | 291 | #define IRQ_PH5 BFIN_PH_IRQ(5) |
292 | #define IRQ_PH5 BFIN_PH_IRQ(5) | 292 | #define IRQ_PH6 BFIN_PH_IRQ(6) |
293 | #define IRQ_PH6 BFIN_PH_IRQ(6) | 293 | #define IRQ_PH7 BFIN_PH_IRQ(7) |
294 | #define IRQ_PH7 BFIN_PH_IRQ(7) | 294 | #define IRQ_PH8 BFIN_PH_IRQ(8) |
295 | #define IRQ_PH8 BFIN_PH_IRQ(8) | 295 | #define IRQ_PH9 BFIN_PH_IRQ(9) |
296 | #define IRQ_PH9 BFIN_PH_IRQ(9) | 296 | #define IRQ_PH10 BFIN_PH_IRQ(10) |
297 | #define IRQ_PH10 BFIN_PH_IRQ(10) | 297 | #define IRQ_PH11 BFIN_PH_IRQ(11) |
298 | #define IRQ_PH11 BFIN_PH_IRQ(11) | 298 | #define IRQ_PH12 BFIN_PH_IRQ(12) |
299 | #define IRQ_PH12 BFIN_PH_IRQ(12) | 299 | #define IRQ_PH13 BFIN_PH_IRQ(13) |
300 | #define IRQ_PH13 BFIN_PH_IRQ(13) | 300 | #define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ |
301 | #define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ | 301 | #define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ |
302 | #define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ | 302 | |
303 | 303 | #define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) | |
304 | #define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) | 304 | #define IRQ_PI0 BFIN_PI_IRQ(0) |
305 | #define IRQ_PI0 BFIN_PI_IRQ(0) | 305 | #define IRQ_PI1 BFIN_PI_IRQ(1) |
306 | #define IRQ_PI1 BFIN_PI_IRQ(1) | 306 | #define IRQ_PI2 BFIN_PI_IRQ(2) |
307 | #define IRQ_PI2 BFIN_PI_IRQ(2) | 307 | #define IRQ_PI3 BFIN_PI_IRQ(3) |
308 | #define IRQ_PI3 BFIN_PI_IRQ(3) | 308 | #define IRQ_PI4 BFIN_PI_IRQ(4) |
309 | #define IRQ_PI4 BFIN_PI_IRQ(4) | 309 | #define IRQ_PI5 BFIN_PI_IRQ(5) |
310 | #define IRQ_PI5 BFIN_PI_IRQ(5) | 310 | #define IRQ_PI6 BFIN_PI_IRQ(6) |
311 | #define IRQ_PI6 BFIN_PI_IRQ(6) | 311 | #define IRQ_PI7 BFIN_PI_IRQ(7) |
312 | #define IRQ_PI7 BFIN_PI_IRQ(7) | 312 | #define IRQ_PI8 BFIN_PI_IRQ(8) |
313 | #define IRQ_PI8 BFIN_PI_IRQ(8) | 313 | #define IRQ_PI9 BFIN_PI_IRQ(9) |
314 | #define IRQ_PI9 BFIN_PI_IRQ(9) | 314 | #define IRQ_PI10 BFIN_PI_IRQ(10) |
315 | #define IRQ_PI10 BFIN_PI_IRQ(10) | 315 | #define IRQ_PI11 BFIN_PI_IRQ(11) |
316 | #define IRQ_PI11 BFIN_PI_IRQ(11) | 316 | #define IRQ_PI12 BFIN_PI_IRQ(12) |
317 | #define IRQ_PI12 BFIN_PI_IRQ(12) | 317 | #define IRQ_PI13 BFIN_PI_IRQ(13) |
318 | #define IRQ_PI13 BFIN_PI_IRQ(13) | 318 | #define IRQ_PI14 BFIN_PI_IRQ(14) |
319 | #define IRQ_PI14 BFIN_PI_IRQ(14) | 319 | #define IRQ_PI15 BFIN_PI_IRQ(15) |
320 | #define IRQ_PI15 BFIN_PI_IRQ(15) | 320 | |
321 | 321 | #define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) | |
322 | #define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) | 322 | #define IRQ_PJ0 BFIN_PJ_IRQ(0) |
323 | #define IRQ_PJ0 BFIN_PJ_IRQ(0) | 323 | #define IRQ_PJ1 BFIN_PJ_IRQ(1) |
324 | #define IRQ_PJ1 BFIN_PJ_IRQ(1) | 324 | #define IRQ_PJ2 BFIN_PJ_IRQ(2) |
325 | #define IRQ_PJ2 BFIN_PJ_IRQ(2) | 325 | #define IRQ_PJ3 BFIN_PJ_IRQ(3) |
326 | #define IRQ_PJ3 BFIN_PJ_IRQ(3) | 326 | #define IRQ_PJ4 BFIN_PJ_IRQ(4) |
327 | #define IRQ_PJ4 BFIN_PJ_IRQ(4) | 327 | #define IRQ_PJ5 BFIN_PJ_IRQ(5) |
328 | #define IRQ_PJ5 BFIN_PJ_IRQ(5) | 328 | #define IRQ_PJ6 BFIN_PJ_IRQ(6) |
329 | #define IRQ_PJ6 BFIN_PJ_IRQ(6) | 329 | #define IRQ_PJ7 BFIN_PJ_IRQ(7) |
330 | #define IRQ_PJ7 BFIN_PJ_IRQ(7) | 330 | #define IRQ_PJ8 BFIN_PJ_IRQ(8) |
331 | #define IRQ_PJ8 BFIN_PJ_IRQ(8) | 331 | #define IRQ_PJ9 BFIN_PJ_IRQ(9) |
332 | #define IRQ_PJ9 BFIN_PJ_IRQ(9) | 332 | #define IRQ_PJ10 BFIN_PJ_IRQ(10) |
333 | #define IRQ_PJ10 BFIN_PJ_IRQ(10) | 333 | #define IRQ_PJ11 BFIN_PJ_IRQ(11) |
334 | #define IRQ_PJ11 BFIN_PJ_IRQ(11) | 334 | #define IRQ_PJ12 BFIN_PJ_IRQ(12) |
335 | #define IRQ_PJ12 BFIN_PJ_IRQ(12) | 335 | #define IRQ_PJ13 BFIN_PJ_IRQ(13) |
336 | #define IRQ_PJ13 BFIN_PJ_IRQ(13) | 336 | #define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ |
337 | #define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ | 337 | #define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ |
338 | #define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ | 338 | |
339 | #define GPIO_IRQ_BASE IRQ_PA0 | ||
339 | 340 | ||
340 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | 341 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO |
341 | #define NR_IRQS (IRQ_PJ15+1) | 342 | #define NR_IRQS (IRQ_PJ15+1) |
@@ -343,6 +344,34 @@ Events (highest priority) EMU 0 | |||
343 | #define NR_IRQS (SYS_IRQS+1) | 344 | #define NR_IRQS (SYS_IRQS+1) |
344 | #endif | 345 | #endif |
345 | 346 | ||
347 | /* For compatibility reasons with existing code */ | ||
348 | |||
349 | #define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR | ||
350 | #define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR | ||
351 | #define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR | ||
352 | #define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR | ||
353 | #define IRQ_SPI0_ERR IRQ_SPI0_ERROR | ||
354 | #define IRQ_UART0_ERR IRQ_UART0_ERROR | ||
355 | #define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR | ||
356 | #define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR | ||
357 | #define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR | ||
358 | #define IRQ_SPI1_ERR IRQ_SPI1_ERROR | ||
359 | #define IRQ_SPI2_ERR IRQ_SPI2_ERROR | ||
360 | #define IRQ_UART1_ERR IRQ_UART1_ERROR | ||
361 | #define IRQ_UART2_ERR IRQ_UART2_ERROR | ||
362 | #define IRQ_CAN0_ERR IRQ_CAN0_ERROR | ||
363 | #define IRQ_MXVR_ERR IRQ_MXVR_ERROR | ||
364 | #define IRQ_EPP1_ERR IRQ_EPP1_ERROR | ||
365 | #define IRQ_EPP2_ERR IRQ_EPP2_ERROR | ||
366 | #define IRQ_UART3_ERR IRQ_UART3_ERROR | ||
367 | #define IRQ_HOST_ERR IRQ_HOST_ERROR | ||
368 | #define IRQ_PIXC_ERR IRQ_PIXC_ERROR | ||
369 | #define IRQ_NFC_ERR IRQ_NFC_ERROR | ||
370 | #define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR | ||
371 | #define IRQ_CAN1_ERR IRQ_CAN1_ERROR | ||
372 | #define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR | ||
373 | |||
374 | |||
346 | #define IVG7 7 | 375 | #define IVG7 7 |
347 | #define IVG8 8 | 376 | #define IVG8 8 |
348 | #define IVG9 9 | 377 | #define IVG9 9 |
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h index 72d80e8a6e81..ec1597e31831 100644 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ b/include/asm-blackfin/mach-bf548/mem_map.h | |||
@@ -51,10 +51,10 @@ | |||
51 | /* Level 1 Memory */ | 51 | /* Level 1 Memory */ |
52 | 52 | ||
53 | /* Memory Map for ADSP-BF548 processors */ | 53 | /* Memory Map for ADSP-BF548 processors */ |
54 | #ifdef CONFIG_BLKFIN_ICACHE | 54 | #ifdef CONFIG_BFIN_ICACHE |
55 | #define BLKFIN_ICACHESIZE (16*1024) | 55 | #define BFIN_ICACHESIZE (16*1024) |
56 | #else | 56 | #else |
57 | #define BLKFIN_ICACHESIZE (0*1024) | 57 | #define BFIN_ICACHESIZE (0*1024) |
58 | #endif | 58 | #endif |
59 | 59 | ||
60 | #define L1_CODE_START 0xFFA00000 | 60 | #define L1_CODE_START 0xFFA00000 |
@@ -63,29 +63,29 @@ | |||
63 | 63 | ||
64 | #define L1_CODE_LENGTH 0xC000 | 64 | #define L1_CODE_LENGTH 0xC000 |
65 | 65 | ||
66 | #ifdef CONFIG_BLKFIN_DCACHE | 66 | #ifdef CONFIG_BFIN_DCACHE |
67 | 67 | ||
68 | #ifdef CONFIG_BLKFIN_DCACHE_BANKA | 68 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
69 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | 69 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
70 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 70 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
71 | #define L1_DATA_B_LENGTH 0x8000 | 71 | #define L1_DATA_B_LENGTH 0x8000 |
72 | #define BLKFIN_DCACHESIZE (16*1024) | 72 | #define BFIN_DCACHESIZE (16*1024) |
73 | #define BLKFIN_DSUPBANKS 1 | 73 | #define BFIN_DSUPBANKS 1 |
74 | #else | 74 | #else |
75 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | 75 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
76 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 76 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
77 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | 77 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) |
78 | #define BLKFIN_DCACHESIZE (32*1024) | 78 | #define BFIN_DCACHESIZE (32*1024) |
79 | #define BLKFIN_DSUPBANKS 2 | 79 | #define BFIN_DSUPBANKS 2 |
80 | #endif | 80 | #endif |
81 | 81 | ||
82 | #else | 82 | #else |
83 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | 83 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
84 | #define L1_DATA_A_LENGTH 0x8000 | 84 | #define L1_DATA_A_LENGTH 0x8000 |
85 | #define L1_DATA_B_LENGTH 0x8000 | 85 | #define L1_DATA_B_LENGTH 0x8000 |
86 | #define BLKFIN_DCACHESIZE (0*1024) | 86 | #define BFIN_DCACHESIZE (0*1024) |
87 | #define BLKFIN_DSUPBANKS 0 | 87 | #define BFIN_DSUPBANKS 0 |
88 | #endif /*CONFIG_BLKFIN_DCACHE*/ | 88 | #endif /*CONFIG_BFIN_DCACHE*/ |
89 | 89 | ||
90 | /* Scratch Pad Memory */ | 90 | /* Scratch Pad Memory */ |
91 | 91 | ||