diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2007-12-23 10:02:13 -0500 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-12-23 10:02:13 -0500 |
| commit | fb5f00492a748facc9f069c95621e05c148edf53 (patch) | |
| tree | cf93dbf8140279e4913eb421dd68922a76ba241f /include/asm-blackfin/mach-bf548/irq.h | |
| parent | c50e19f49830fb651b4b702ad2c3abcdf110b576 (diff) | |
[Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM.
On BF548-EZKIT, build kernel faills with power management, video and audio enabled.
This patch fix this.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548/irq.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/irq.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 9fb7bc5399a8..c34507a3f1df 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h | |||
| @@ -88,7 +88,7 @@ Events (highest priority) EMU 0 | |||
| 88 | #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ | 88 | #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ |
| 89 | #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ | 89 | #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ |
| 90 | #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ | 90 | #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ |
| 91 | #define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ | 91 | #define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ |
| 92 | #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ | 92 | #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ |
| 93 | #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ | 93 | #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ |
| 94 | #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ | 94 | #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ |
| @@ -406,7 +406,7 @@ Events (highest priority) EMU 0 | |||
| 406 | #define IRQ_PINT1_POS 16 | 406 | #define IRQ_PINT1_POS 16 |
| 407 | #define IRQ_MDMAS0_POS 20 | 407 | #define IRQ_MDMAS0_POS 20 |
| 408 | #define IRQ_MDMAS1_POS 24 | 408 | #define IRQ_MDMAS1_POS 24 |
| 409 | #define IRQ_WATCHDOG_POS 28 | 409 | #define IRQ_WATCH_POS 28 |
| 410 | 410 | ||
| 411 | /* IAR3 BIT FIELDS */ | 411 | /* IAR3 BIT FIELDS */ |
| 412 | #define IRQ_DMAC1_ERR_POS 0 | 412 | #define IRQ_DMAC1_ERR_POS 0 |