diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2008-02-02 03:31:00 -0500 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2008-02-02 03:31:00 -0500 |
| commit | 8b01eaff4fdf39d23d53288fd1a3e74fef136145 (patch) | |
| tree | 819a0e86598a75860fc2ed0c23a51f02957cee6c /include/asm-blackfin/mach-bf548/irq.h | |
| parent | 83d9cde08b72233d113e31ab93b6b56151be8719 (diff) | |
[Blackfin] arch: Enable UART2 and UART3 for bf548
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548/irq.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/irq.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index c34507a3f1df..ad380d1f5872 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h | |||
| @@ -99,9 +99,13 @@ Events (highest priority) EMU 0 | |||
| 99 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ | 99 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ |
| 100 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ | 100 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ |
| 101 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ | 101 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ |
| 102 | #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ | ||
| 102 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ | 103 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ |
| 104 | #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ | ||
| 103 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ | 105 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ |
| 106 | #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ | ||
| 104 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ | 107 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ |
| 108 | #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ | ||
| 105 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ | 109 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ |
| 106 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ | 110 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ |
| 107 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ | 111 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ |
| @@ -421,9 +425,13 @@ Events (highest priority) EMU 0 | |||
| 421 | /* IAR4 BIT FILEDS */ | 425 | /* IAR4 BIT FILEDS */ |
| 422 | #define IRQ_CAN0_ERR_POS 0 | 426 | #define IRQ_CAN0_ERR_POS 0 |
| 423 | #define IRQ_SPORT2_RX_POS 4 | 427 | #define IRQ_SPORT2_RX_POS 4 |
| 428 | #define IRQ_UART2_RX_POS 4 | ||
| 424 | #define IRQ_SPORT2_TX_POS 8 | 429 | #define IRQ_SPORT2_TX_POS 8 |
| 430 | #define IRQ_UART2_TX_POS 8 | ||
| 425 | #define IRQ_SPORT3_RX_POS 12 | 431 | #define IRQ_SPORT3_RX_POS 12 |
| 432 | #define IRQ_UART3_RX_POS 12 | ||
| 426 | #define IRQ_SPORT3_TX_POS 16 | 433 | #define IRQ_SPORT3_TX_POS 16 |
| 434 | #define IRQ_UART3_TX_POS 16 | ||
| 427 | #define IRQ_EPPI1_POS 20 | 435 | #define IRQ_EPPI1_POS 20 |
| 428 | #define IRQ_EPPI2_POS 24 | 436 | #define IRQ_EPPI2_POS 24 |
| 429 | #define IRQ_SPI1_POS 28 | 437 | #define IRQ_SPI1_POS 28 |