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authorMichael Hennerich <michael.hennerich@analog.com>2008-07-14 04:51:57 -0400
committerBryan Wu <cooloney@kernel.org>2008-07-14 04:51:57 -0400
commit68e2fc78e5055740126df8eab0d31005495756c9 (patch)
tree0d43976ff1d3ae8535445f9bcb1687f657f33337 /include/asm-blackfin/mach-bf533/mem_init.h
parent260d5d3517c67c5b68b4e28c5d3e1e3b73976a90 (diff)
Blackfin arch: Fix bug - Kernel does not boot if re-program clocks
Don't write conflicting data to EBIU_SDBCTL after the SDRAM is configured. This can cause data corruption, since we might change SDRAM row and column addressing modes. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/mem_init.h')
-rw-r--r--include/asm-blackfin/mach-bf533/mem_init.h27
1 files changed, 0 insertions, 27 deletions
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
index f8f31901fca9..995c06b2b1ef 100644
--- a/include/asm-blackfin/mach-bf533/mem_init.h
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -133,33 +133,6 @@
133#define SDRAM_CL CL_3 133#define SDRAM_CL CL_3
134#endif 134#endif
135 135
136#if (CONFIG_MEM_SIZE == 128)
137#define SDRAM_SIZE EBSZ_128
138#endif
139#if (CONFIG_MEM_SIZE == 64)
140#define SDRAM_SIZE EBSZ_64
141#endif
142#if (CONFIG_MEM_SIZE == 32)
143#define SDRAM_SIZE EBSZ_32
144#endif
145#if (CONFIG_MEM_SIZE == 16)
146#define SDRAM_SIZE EBSZ_16
147#endif
148#if (CONFIG_MEM_ADD_WIDTH == 11)
149#define SDRAM_WIDTH EBCAW_11
150#endif
151#if (CONFIG_MEM_ADD_WIDTH == 10)
152#define SDRAM_WIDTH EBCAW_10
153#endif
154#if (CONFIG_MEM_ADD_WIDTH == 9)
155#define SDRAM_WIDTH EBCAW_9
156#endif
157#if (CONFIG_MEM_ADD_WIDTH == 8)
158#define SDRAM_WIDTH EBCAW_8
159#endif
160
161#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
162
163/* Equation from section 17 (p17-46) of BF533 HRM */ 136/* Equation from section 17 (p17-46) of BF533 HRM */
164#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) 137#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
165 138