diff options
author | Michael Hennerich <michael.hennerich@analog.com> | 2008-05-09 12:11:59 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-05-09 12:11:59 -0400 |
commit | 56f87713022a6bdf00b0a50d086fdaddb54e8e5c (patch) | |
tree | 7687e2bcf5bcad67f14367f4208e001cd490010c /include/asm-blackfin/mach-bf533/irq.h | |
parent | e4f7c0bf1f2e8a1b184a33ab60e874391d70f86c (diff) |
[Blackfin] arch: remove useless IRQ_SW_INT defines
IRQ_SW_INT1 and IRQ_SW_INT2 obsolete:
Remove useless defines
Fix SYS_IRQS
Keep numbering scheme, so we don't break existing configurations.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/irq.h')
-rw-r--r-- | include/asm-blackfin/mach-bf533/irq.h | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h index 832e6f6122da..5aa38e5da6b7 100644 --- a/include/asm-blackfin/mach-bf533/irq.h +++ b/include/asm-blackfin/mach-bf533/irq.h | |||
@@ -66,12 +66,13 @@ Core Emulation ** | |||
66 | DMA8/9 Interrupt IVG13 28 | 66 | DMA8/9 Interrupt IVG13 28 |
67 | DMA10/11 Interrupt IVG13 29 | 67 | DMA10/11 Interrupt IVG13 29 |
68 | Watchdog Timer IVG13 30 | 68 | Watchdog Timer IVG13 30 |
69 | Software Interrupt 1 IVG14 31 | 69 | |
70 | Software Interrupt 2 -- | 70 | Softirq IVG14 31 |
71 | System Call -- | ||
71 | (lowest priority) IVG15 32 * | 72 | (lowest priority) IVG15 32 * |
72 | */ | 73 | */ |
73 | #define SYS_IRQS 32 | 74 | #define SYS_IRQS 31 |
74 | #define NR_PERI_INTS 24 | 75 | #define NR_PERI_INTS 24 |
75 | 76 | ||
76 | /* The ABSTRACT IRQ definitions */ | 77 | /* The ABSTRACT IRQ definitions */ |
77 | /** the first seven of the following are fixed, the rest you change if you need to **/ | 78 | /** the first seven of the following are fixed, the rest you change if you need to **/ |
@@ -96,7 +97,7 @@ Core Emulation ** | |||
96 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ | 97 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ |
97 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ | 98 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ |
98 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ | 99 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ |
99 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ | 100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ |
100 | #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ | 101 | #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ |
101 | #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ | 102 | #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ |
102 | #define IRQ_TMR0 23 /*Timer 0 */ | 103 | #define IRQ_TMR0 23 /*Timer 0 */ |
@@ -108,9 +109,6 @@ Core Emulation ** | |||
108 | #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ | 109 | #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ |
109 | #define IRQ_WATCH 30 /*Watch Dog Timer */ | 110 | #define IRQ_WATCH 30 /*Watch Dog Timer */ |
110 | 111 | ||
111 | #define IRQ_SW_INT1 31 /*Software Int 1 */ | ||
112 | #define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */ | ||
113 | |||
114 | #define IRQ_PF0 33 | 112 | #define IRQ_PF0 33 |
115 | #define IRQ_PF1 34 | 113 | #define IRQ_PF1 34 |
116 | #define IRQ_PF2 35 | 114 | #define IRQ_PF2 35 |