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authorBryan Wu <bryan.wu@analog.com>2007-05-21 06:09:31 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-21 12:50:23 -0400
commit19381f024b01413d83cec1655c3fc4c9c09ae274 (patch)
tree4ba1d63900e031c97130638c2d678aaf15c3d37e /include/asm-blackfin/mach-bf533/defBF532.h
parentc09c4e006590210001ced90d59e62182bfd396f9 (diff)
Blackfin arch: update blackfin header files to latest one in VDSP.
a) add new processor BF52x/BF54x header files b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP. c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/defBF532.h')
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h207
1 files changed, 145 insertions, 62 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index b240a082aa09..6a3cf93f8b57 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -46,11 +46,7 @@
46 46
47#ifndef _DEF_BF532_H 47#ifndef _DEF_BF532_H
48#define _DEF_BF532_H 48#define _DEF_BF532_H
49/* 49
50#if !defined(__ADSPLPBLACKFIN__)
51#warning defBF532.h should only be included for 532 compatible chips
52#endif
53*/
54/* include all Core registers and bit definitions */ 50/* include all Core registers and bit definitions */
55#include <asm/mach-common/def_LPBlackfin.h> 51#include <asm/mach-common/def_LPBlackfin.h>
56 52
@@ -65,10 +61,10 @@
65#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 61#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
66#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 62#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
67#define CHIPID 0xFFC00014 /* Chip ID Register */ 63#define CHIPID 0xFFC00014 /* Chip ID Register */
68#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
69#define SYSCR 0xFFC00104 /* System Configuration registe */
70 64
71/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 65/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
66#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
67#define SYSCR 0xFFC00104 /* System Configuration registe */
72#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ 68#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
73#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ 69#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
74#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 70#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
@@ -218,11 +214,13 @@
218#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 214#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
219 215
220/* DMA Traffic controls */ 216/* DMA Traffic controls */
221#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 217#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 218#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225 219
220/* Alternate deprecated register names (below) provided for backwards code compatibility */
221#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223
226/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 224/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
227#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 225#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
228#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 226#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -407,14 +405,25 @@
407/* ********************* PLL AND RESET MASKS ************************ */ 405/* ********************* PLL AND RESET MASKS ************************ */
408 406
409/* PLL_CTL Masks */ 407/* PLL_CTL Masks */
410#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ 408#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
411#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ 409#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
412#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ 410#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
413#define STOPCK_OFF 0x00000008 /* Core clock off */ 411#define PLL_OFF 0x0002 /* Shut off PLL clocks */
414#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ 412#define STOPCK_OFF 0x0008 /* Core clock off */
415#define BYPASS 0x00000100 /* Bypass the PLL */ 413#define STOPCK 0x0008 /* Core Clock Off */
414#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
415#if !defined(__ADSPBF538__)
416/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
417# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
418# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
419#endif
420#define BYPASS 0x0100 /* Bypass the PLL */
421/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
422#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
416 423
417/* PLL_DIV Masks */ 424/* PLL_DIV Masks */
425#define SSEL 0x000F /* System Select */
426#define CSEL 0x0030 /* Core Select */
418 427
419#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 428#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
420 429
@@ -422,6 +431,8 @@
422#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ 431#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
423#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ 432#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
424#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ 433#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
434/* PLL_DIV Macros */
435#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
425 436
426/* PLL_STAT Masks */ 437/* PLL_STAT Masks */
427#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 438#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
@@ -429,13 +440,47 @@
429#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 440#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
430#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 441#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
431 442
443/* VR_CTL Masks */
444#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
445#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
446#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
447#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
448#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
449
450#define GAIN 0x000C /* Voltage Level Gain */
451#define GAIN_5 0x0000 /* GAIN = 5 */
452#define GAIN_10 0x0004 /* GAIN = 10 */
453#define GAIN_20 0x0008 /* GAIN = 20 */
454#define GAIN_50 0x000C /* GAIN = 50 */
455
456#define VLEV 0x00F0 /* Internal Voltage Level */
457#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
458#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
459#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
460#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
461#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
462#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
463#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
464#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
465
466#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
467#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
468
432/* CHIPID Masks */ 469/* CHIPID Masks */
433#define CHIPID_VERSION 0xF0000000 470#define CHIPID_VERSION 0xF0000000
434#define CHIPID_FAMILY 0x0FFFF000 471#define CHIPID_FAMILY 0x0FFFF000
435#define CHIPID_MANUFACTURE 0x00000FFE 472#define CHIPID_MANUFACTURE 0x00000FFE
436 473
437/* SWRST Mask */ 474/* SWRST Mask */
438#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ 475#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
476#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
477#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
478#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
479#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
480
481/* SYSCR Masks */
482#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
483#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
439 484
440/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 485/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
441 486
@@ -483,23 +528,6 @@
483#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 528#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
484#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 529#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
485 530
486/* ********* WATCHDOG TIMER MASKS ********************8 */
487
488/* Watchdog Timer WDOG_CTL Register */
489#define ICTL(x) ((x<<1) & 0x0006)
490#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
491#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
492#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
493#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
494
495#define TMR_EN 0x0000
496#define TMR_DIS 0x0AD0
497#define TRO 0x8000
498
499#define ICTL_P0 0x01
500#define ICTL_P1 0x02
501#define TRO_P 0x0F
502
503/* ***************************** UART CONTROLLER MASKS ********************** */ 531/* ***************************** UART CONTROLLER MASKS ********************** */
504 532
505/* UART_LCR Register */ 533/* UART_LCR Register */
@@ -583,6 +611,9 @@
583#define TSPEN 0x0001 /* TX enable */ 611#define TSPEN 0x0001 /* TX enable */
584#define ITCLK 0x0002 /* Internal TX Clock Select */ 612#define ITCLK 0x0002 /* Internal TX Clock Select */
585#define TDTYPE 0x000C /* TX Data Formatting Select */ 613#define TDTYPE 0x000C /* TX Data Formatting Select */
614#define DTYPE_NORM 0x0000 /* Data Format Normal */
615#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
616#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
586#define TLSBIT 0x0010 /* TX Bit Order */ 617#define TLSBIT 0x0010 /* TX Bit Order */
587#define ITFS 0x0200 /* Internal TX Frame Sync Select */ 618#define ITFS 0x0200 /* Internal TX Frame Sync Select */
588#define TFSR 0x0400 /* TX Frame Sync Required Select */ 619#define TFSR 0x0400 /* TX Frame Sync Required Select */
@@ -592,7 +623,12 @@
592#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ 623#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
593 624
594/* SPORTx_TCR2 Masks */ 625/* SPORTx_TCR2 Masks */
595#define SLEN 0x001F /*TX Word Length */ 626#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
627 defined(__ADSPBF533__)
628# define SLEN 0x001F /*TX Word Length */
629#else
630# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
631#endif
596#define TXSE 0x0100 /*TX Secondary Enable */ 632#define TXSE 0x0100 /*TX Secondary Enable */
597#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ 633#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
598#define TRFST 0x0400 /*TX Right-First Data Order */ 634#define TRFST 0x0400 /*TX Right-First Data Order */
@@ -601,8 +637,9 @@
601#define RSPEN 0x0001 /* RX enable */ 637#define RSPEN 0x0001 /* RX enable */
602#define IRCLK 0x0002 /* Internal RX Clock Select */ 638#define IRCLK 0x0002 /* Internal RX Clock Select */
603#define RDTYPE 0x000C /* RX Data Formatting Select */ 639#define RDTYPE 0x000C /* RX Data Formatting Select */
604#define RULAW 0x0008 /* u-Law enable */ 640#define DTYPE_NORM 0x0000 /* no companding */
605#define RALAW 0x000C /* A-Law enable */ 641#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
642#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
606#define RLSBIT 0x0010 /* RX Bit Order */ 643#define RLSBIT 0x0010 /* RX Bit Order */
607#define IRFS 0x0200 /* Internal RX Frame Sync Select */ 644#define IRFS 0x0200 /* Internal RX Frame Sync Select */
608#define RFSR 0x0400 /* RX Frame Sync Required Select */ 645#define RFSR 0x0400 /* RX Frame Sync Required Select */
@@ -611,7 +648,7 @@
611#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ 648#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
612 649
613/* SPORTx_RCR2 Masks */ 650/* SPORTx_RCR2 Masks */
614#define SLEN 0x001F /*RX Word Length */ 651/* SLEN defined above */
615#define RXSE 0x0100 /*RX Secondary Enable */ 652#define RXSE 0x0100 /*RX Secondary Enable */
616#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ 653#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
617#define RRFST 0x0400 /*Right-First Data Order */ 654#define RRFST 0x0400 /*Right-First Data Order */
@@ -628,14 +665,37 @@
628/*SPORTx_MCMC1 Masks */ 665/*SPORTx_MCMC1 Masks */
629#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ 666#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
630#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ 667#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
668/* SPORTx_MCMC1 Macros */
669#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
670/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
671#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
631 672
632/*SPORTx_MCMC2 Masks */ 673/*SPORTx_MCMC2 Masks */
633#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ 674#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
634#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ 675#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
635#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ 676#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
636#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ 677#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
637#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ 678#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
638#define MFD 0x0000F000 /*Multichannel Frame Delay */ 679#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
680#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
681#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
682#define MFD 0x0000F000 /*Multichannel Frame Delay */
683#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
684#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
685#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
686#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
687#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
688#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
689#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
690#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
691#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
692#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
693#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
694#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
695#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
696#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
697#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
698#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
639 699
640/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 700/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
641 701
@@ -660,6 +720,8 @@
660#define DLEN_16 0x3800 /* Data Length = 16 Bits */ 720#define DLEN_16 0x3800 /* Data Length = 16 Bits */
661#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 721#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
662#define POL 0x0000C000 /* PPI Signal Polarities */ 722#define POL 0x0000C000 /* PPI Signal Polarities */
723#define POLC 0x4000 /* PPI Clock Polarity */
724#define POLS 0x8000 /* PPI Frame Sync Polarity */
663 725
664/* PPI_STATUS Masks */ 726/* PPI_STATUS Masks */
665#define FLD 0x00000400 /* Field Indicator */ 727#define FLD 0x00000400 /* Field Indicator */
@@ -729,6 +791,15 @@
729#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ 791#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
730#define PMAP 0x00007000 /* DMA Peripheral Map Field */ 792#define PMAP 0x00007000 /* DMA Peripheral Map Field */
731 793
794#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
795#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
796#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
797#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
798#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
799#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
800#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
801#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
802
732/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ 803/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
733 804
734/* PWM Timer bit definitions */ 805/* PWM Timer bit definitions */
@@ -755,9 +826,9 @@
755#define TIMIL0 0x0001 826#define TIMIL0 0x0001
756#define TIMIL1 0x0002 827#define TIMIL1 0x0002
757#define TIMIL2 0x0004 828#define TIMIL2 0x0004
758#define TOVL_ERR0 0x0010 829#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
759#define TOVL_ERR1 0x0020 830#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
760#define TOVL_ERR2 0x0040 831#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
761#define TRUN0 0x1000 832#define TRUN0 0x1000
762#define TRUN1 0x2000 833#define TRUN1 0x2000
763#define TRUN2 0x4000 834#define TRUN2 0x4000
@@ -765,13 +836,21 @@
765#define TIMIL0_P 0x00 836#define TIMIL0_P 0x00
766#define TIMIL1_P 0x01 837#define TIMIL1_P 0x01
767#define TIMIL2_P 0x02 838#define TIMIL2_P 0x02
768#define TOVL_ERR0_P 0x04 839#define TOVF_ERR0_P 0x04
769#define TOVL_ERR1_P 0x05 840#define TOVF_ERR1_P 0x05
770#define TOVL_ERR2_P 0x06 841#define TOVF_ERR2_P 0x06
771#define TRUN0_P 0x0C 842#define TRUN0_P 0x0C
772#define TRUN1_P 0x0D 843#define TRUN1_P 0x0D
773#define TRUN2_P 0x0E 844#define TRUN2_P 0x0E
774 845
846/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
847#define TOVL_ERR0 TOVF_ERR0
848#define TOVL_ERR1 TOVF_ERR1
849#define TOVL_ERR2 TOVF_ERR2
850#define TOVL_ERR0_P TOVF_ERR0_P
851#define TOVL_ERR1_P TOVF_ERR1_P
852#define TOVL_ERR2_P TOVF_ERR2_P
853
775/* TIMERx_CONFIG Registers */ 854/* TIMERx_CONFIG Registers */
776#define PWM_OUT 0x0001 855#define PWM_OUT 0x0001
777#define WDTH_CAP 0x0002 856#define WDTH_CAP 0x0002
@@ -841,6 +920,10 @@
841 920
842/* SPI_CTL Masks */ 921/* SPI_CTL Masks */
843#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ 922#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
923#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
924#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
925#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
926#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
844#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ 927#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
845#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ 928#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
846#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ 929#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
@@ -894,10 +977,20 @@
894#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ 977#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
895#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ 978#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
896 979
980/* SPIx_FLG Masks */
981#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
982#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
983#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
984#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
985#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
986#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
987#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
988
897/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 989/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
898 990
899/* AMGCTL Masks */ 991/* AMGCTL Masks */
900#define AMCKEN 0x00000001 /* Enable CLKOUT */ 992#define AMCKEN 0x00000001 /* Enable CLKOUT */
993#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
901#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ 994#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
902#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ 995#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
903#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ 996#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
@@ -1097,6 +1190,9 @@
1097#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ 1190#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1098#define PFE 0x00000010 /* Enable SDRAM prefetch */ 1191#define PFE 0x00000010 /* Enable SDRAM prefetch */
1099#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ 1192#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1193#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1194#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1195#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1100#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 1196#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1101#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 1197#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1102#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 1198#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
@@ -1158,18 +1254,5 @@
1158#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1254#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1159#define BGSTAT 0x00000020 /* Bus granted */ 1255#define BGSTAT 0x00000020 /* Bus granted */
1160 1256
1161/*VR_CTL Masks*/
1162#define WAKE 0x100
1163#define VLEV_6 0x60
1164#define VLEV_7 0x70
1165#define VLEV_8 0x80
1166#define VLEV_9 0x90
1167#define VLEV_10 0xA0
1168#define VLEV_11 0xB0
1169#define VLEV_12 0xC0
1170#define VLEV_13 0xD0
1171#define VLEV_14 0xE0
1172#define VLEV_15 0xF0
1173#define FREQ_3 0x03
1174 1257
1175#endif /* _DEF_BF532_H */ 1258#endif /* _DEF_BF532_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 05:14:41 -0500