[PATCH] avr32 architecture

This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.

AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density.  The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.

The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf

The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture.  It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit.  It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.

Full data sheet is available from

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf

while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

Information about the AT32STK1000 development board can be found at

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918

including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.

Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.

This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.

[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 78 insertions, 0 deletions

diff --git a/include/asm-avr32/ocd.h b/include/asm-avr32/ocd.h
new file mode 100644
index 000000000000..46f73180a127
--- /dev/null
+++ b/include/asm-avr32/ocd.h
@@ -0,0 +1,78 @@
+/*
+ * AVR32 OCD Registers
+ *
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_AVR32_OCD_H
+#define __ASM_AVR32_OCD_H
+
+/* Debug Registers */
+#define DBGREG_DID                0
+#define DBGREG_DC                 8
+#define DBGREG_DS                16
+#define DBGREG_RWCS              28
+#define DBGREG_RWA               36
+#define DBGREG_RWD               40
+#define DBGREG_WT                44
+#define DBGREG_DTC               52
+#define DBGREG_DTSA0             56
+#define DBGREG_DTSA1             60
+#define DBGREG_DTEA0             72
+#define DBGREG_DTEA1             76
+#define DBGREG_BWC0A             88
+#define DBGREG_BWC0B             92
+#define DBGREG_BWC1A             96
+#define DBGREG_BWC1B            100
+#define DBGREG_BWC2A            104
+#define DBGREG_BWC2B            108
+#define DBGREG_BWC3A            112
+#define DBGREG_BWC3B            116
+#define DBGREG_BWA0A            120
+#define DBGREG_BWA0B            124
+#define DBGREG_BWA1A            128
+#define DBGREG_BWA1B            132
+#define DBGREG_BWA2A            136
+#define DBGREG_BWA2B            140
+#define DBGREG_BWA3A            144
+#define DBGREG_BWA3B            148
+#define DBGREG_BWD3A            153
+#define DBGREG_BWD3B            156
+
+#define DBGREG_PID              284
+
+#define SABAH_OCD               0x01
+#define SABAH_ICACHE            0x02
+#define SABAH_MEM_CACHED        0x04
+#define SABAH_MEM_UNCACHED      0x05
+
+/* Fields in the Development Control register */
+#define DC_SS_BIT               8
+
+#define DC_SS                   (1 <<  DC_SS_BIT)
+#define DC_DBE                  (1 << 13)
+#define DC_RID                  (1 << 27)
+#define DC_ORP                  (1 << 28)
+#define DC_MM                   (1 << 29)
+#define DC_RES                  (1 << 30)
+
+/* Fields in the Development Status register */
+#define DS_SSS                  (1 <<  0)
+#define DS_SWB                  (1 <<  1)
+#define DS_HWB                  (1 <<  2)
+#define DS_BP_SHIFT             8
+#define DS_BP_MASK              (0xff << DS_BP_SHIFT)
+
+#define __mfdr(addr)                                                    \
+({                                                                      \
+        register unsigned long value;                                   \
+        asm volatile("mfdr      %0, %1" : "=r"(value) : "i"(addr));     \
+        value;                                                          \
+})
+#define __mtdr(addr, value)                                             \
+        asm volatile("mtdr      %0, %1" : : "i"(addr), "r"(value))
+
+#endif /* __ASM_AVR32_OCD_H */