diff options
author | Ben Dooks <ben-linux@fluff.org> | 2007-02-15 10:28:11 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-15 10:32:58 -0500 |
commit | e9316f9be6bc7cf949a89df6162e25e7fbb867be (patch) | |
tree | 2a1fca7e021fda0a53eb7a379271b8eaa4768c3d /include/asm-arm | |
parent | 092651c5a988ffca98ee26bbb42688fbfd448718 (diff) |
[ARM] 4196/1: S3C24XX: add S3C2410_IRQSUB() to define IRQ for sub-sources
Add a define of S3C2410_IRQSUB() to define all
the sources from the IRQSUB register, to make it
easier to work out the datasheet=>irq mappings
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-s3c2410/irqs.h | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h index 4b7cff456c4e..f28e2d51dc6a 100644 --- a/include/asm-arm/arch-s3c2410/irqs.h +++ b/include/asm-arm/arch-s3c2410/irqs.h | |||
@@ -94,27 +94,30 @@ | |||
94 | * these need to be ordered in number of appearance in the | 94 | * these need to be ordered in number of appearance in the |
95 | * SUBSRC mask register | 95 | * SUBSRC mask register |
96 | */ | 96 | */ |
97 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */ | ||
98 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */ | ||
99 | #define IRQ_S3CUART_ERR0 S3C2410_IRQ(56) | ||
100 | 97 | ||
101 | #define IRQ_S3CUART_RX1 S3C2410_IRQ(57) | 98 | #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) |
102 | #define IRQ_S3CUART_TX1 S3C2410_IRQ(58) | ||
103 | #define IRQ_S3CUART_ERR1 S3C2410_IRQ(59) | ||
104 | 99 | ||
105 | #define IRQ_S3CUART_RX2 S3C2410_IRQ(60) | 100 | #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ |
106 | #define IRQ_S3CUART_TX2 S3C2410_IRQ(61) | 101 | #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) |
107 | #define IRQ_S3CUART_ERR2 S3C2410_IRQ(62) | 102 | #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) |
108 | 103 | ||
109 | #define IRQ_TC S3C2410_IRQ(63) | 104 | #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ |
110 | #define IRQ_ADC S3C2410_IRQ(64) | 105 | #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) |
106 | #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) | ||
107 | |||
108 | #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ | ||
109 | #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) | ||
110 | #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) | ||
111 | |||
112 | #define IRQ_TC S3C2410_IRQSUB(9) | ||
113 | #define IRQ_ADC S3C2410_IRQSUB(10) | ||
111 | 114 | ||
112 | /* extra irqs for s3c2440 */ | 115 | /* extra irqs for s3c2440 */ |
113 | 116 | ||
114 | #define IRQ_S3C2440_CAM_C S3C2410_IRQ(65) | 117 | #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) |
115 | #define IRQ_S3C2440_CAM_P S3C2410_IRQ(66) | 118 | #define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) |
116 | #define IRQ_S3C2440_WDT S3C2410_IRQ(67) | 119 | #define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) |
117 | #define IRQ_S3C2440_AC97 S3C2410_IRQ(68) | 120 | #define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) |
118 | 121 | ||
119 | #define NR_IRQS (IRQ_S3C2440_AC97+1) | 122 | #define NR_IRQS (IRQ_S3C2440_AC97+1) |
120 | 123 | ||